Benchmark

non-incremental/NIA/20190429-UltimateAutomizerSvcomp2019/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i_3.smt2

|
Generated by the tool Ultimate Automizer [1,2] which implements
an automata theoretic approach [3] to software verification.

This SMT script belongs to a set of SMT scripts that was generated by
applying Ultimate Automizer to benchmarks [4] from the SV-COMP 2019 [5,6].
This script might _not_ contain all SMT commands that are used by
Ultimate Automizer. In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2019-04-27, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)

[1] https://ultimate.informatik.uni-freiburg.de/automizer/
[2] Matthias Heizmann, Yu-Fang Chen, Daniel Dietsch, Marius Greitschus,
     Jochen Hoenicke, Yong Li, Alexander Nutz, Betim Musa, Christian
     Schilling, Tanja Schindler, Andreas Podelski: Ultimate Automizer
     and the Search for Perfect Interpolants - (Competition Contribution).
     TACAS (2) 2018: 447-451
[3] Matthias Heizmann, Jochen Hoenicke, Andreas Podelski: Software Model
     Checking for People Who Love Automata. CAV 2013:36-52
[4] https://github.com/sosy-lab/sv-benchmarks
[5] Dirk Beyer: Automatic Verification of C and Java Programs: SV-COMP 2019.
     TACAS (3) 2019: 133-155
[6] https://sv-comp.sosy-lab.org/2019/
|
Benchmark
Size3899
Compressed Size1397
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2020-07-06
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status sat
Size 3891
Compressed Size1398
Max. Term Depth17
Asserts 2
Declared Functions0
Declared Constants2
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

not1 or9 and1 forall5
let17 Int9 mod28 +14
*14 <28 <=8

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2022 0.60 (2/5) cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq unknown ❌ 1200.02000 1193.69000
UltimateEliminator UltimateEliminator+MathSAT-5.6.7-wrapped_default unknown ❌ 1200.03000 1207.09000
Vampire vampire_4.7_smt_fix-wrapped_vampire_smtcomp unknown ❌ 1200.04000 4797.34000
YicesQS yicesQS-2022-07-02-optim-under10_default sat ✅ 0.46829 0.46829
Z3 z3-4.8.17_default unknown ❌ 1200.02000 1199.85000
z3-4.8.11_default sat ✅ 29.34850 29.34350
SMT-COMP 2023 0.57 (3/7) cvc5 cvc5-default-2023-05-16-ea045f305_sq sat ✅ 152.21500 152.20700
iProver iProver-3.8-fix_iprover_SMT unknown ❌ 1200.16000 4751.40000
UltimateEliminator UltimateEliminator+MathSAT-5.6.9_default unknown ❌ 1200.11000 1207.18000
Vampire vampire_4.8_smt_pre_vampire_smtcomp unknown ❌ 1200.08000 4785.18000
YicesQS yicesQS-2022-07-02-optim-under10_default sat ✅ 3.52813 3.52804
Z3 z3-4.8.11_default sat ✅ 0.13582 0.13573
SMT-COMP 2024 0.40 (3/5) Amaya Amaya sat ✅ 4.65949 4.51441
cvc5 cvc5 sat ✅ 0.23329 0.13203
iProver iProver v3.9 unknown ❌ 1201.71735 4777.51809
SMTInterpol SMTInterpol unknown ❌ 11.71814 20.55976
YicesQS YicesQS sat ✅ 17.45140 17.35012
SMT-COMP 2025 0.38 (5/8) Amaya Amaya sat ✅ 3.93269 3.81229
cvc5 cvc5 sat ✅ 0.31861 0.19317
iProver iProver v3.9.3 unknown ❌ 1201.75094 4791.53353
SMTInterpol SMTInterpol unknown ❌ 3.79967 9.48562
UltimateEliminator UltimateEliminator+MathSAT unknown ❌ 1201.75610 1208.33229
YicesQS YicesQS sat ✅ 0.74204 0.61651
Z3alpha Z3-alpha sat ✅ 0.42635 0.46741
Z3 Z3-alpha-base sat ✅ 16.80848 16.67221