Benchmark

non-incremental/NIA/20190429-UltimateAutomizerSvcomp2019/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i_1.smt2

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Generated by the tool Ultimate Automizer [1,2] which implements
an automata theoretic approach [3] to software verification.

This SMT script belongs to a set of SMT scripts that was generated by
applying Ultimate Automizer to benchmarks [4] from the SV-COMP 2019 [5,6].
This script might _not_ contain all SMT commands that are used by
Ultimate Automizer. In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2019-04-27, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)

[1] https://ultimate.informatik.uni-freiburg.de/automizer/
[2] Matthias Heizmann, Yu-Fang Chen, Daniel Dietsch, Marius Greitschus,
     Jochen Hoenicke, Yong Li, Alexander Nutz, Betim Musa, Christian
     Schilling, Tanja Schindler, Andreas Podelski: Ultimate Automizer
     and the Search for Perfect Interpolants - (Competition Contribution).
     TACAS (2) 2018: 447-451
[3] Matthias Heizmann, Jochen Hoenicke, Andreas Podelski: Software Model
     Checking for People Who Love Automata. CAV 2013:36-52
[4] https://github.com/sosy-lab/sv-benchmarks
[5] Dirk Beyer: Automatic Verification of C and Java Programs: SV-COMP 2019.
     TACAS (3) 2019: 133-155
[6] https://sv-comp.sosy-lab.org/2019/
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Benchmark
Size2913
Compressed Size1243
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2020-07-06
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status sat
Size 2905
Compressed Size1248
Max. Term Depth11
Asserts 2
Declared Functions0
Declared Constants1
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

not1 or2 and2 forall2
exists1 let10 Int7 mod14
+8 *6 <11 <=15

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2020 0.33 (4/6) CVC4 CVC4-sq-final_default sat ✅ 336.68100 330.79800
SMTInterpol smtinterpol-2.5-679-gacfde87a_default sat ✅ 20.34390 27.46060
UltimateEliminator UltimateEliminator+MathSAT-5.6.3_s_default sat ✅ 2.39484 3.52975
Vampire vampire_smt_4.5_vampire_smtcomp unknown ❌ 1200.06000 4702.51000
veriT veriT_default unknown ❌ 0.07077 0.07337
veriT+vite_default unknown ❌ 0.01000 0.01022
Z3 z3-4.8.8_default sat ✅ 0.03868 0.03864
z3-4.8.4-d6df51951f4c-wrapped-sq_default sat ✅ 4.80025 4.79932
SMT-COMP 2022 0.40 (3/5) cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq sat ✅ 300.53600 300.24400
UltimateEliminator UltimateEliminator+MathSAT-5.6.7-wrapped_default unknown ❌ 1200.03000 1224.58000
Vampire vampire_4.7_smt_fix-wrapped_vampire_smtcomp unknown ❌ 1200.03000 4757.95000
YicesQS yicesQS-2022-07-02-optim-under10_default sat ✅ 0.12020 0.12025
Z3 z3-4.8.17_default sat ✅ 0.13389 0.13398
z3-4.8.11_default sat ✅ 0.03520 0.03514
SMT-COMP 2023 0.57 (3/7) cvc5 cvc5-default-2023-05-16-ea045f305_sq sat ✅ 300.99400 300.18700
iProver iProver-3.8-fix_iprover_SMT unknown ❌ 1200.08000 4744.34000
UltimateEliminator UltimateEliminator+MathSAT-5.6.9_default unknown ❌ 1200.03000 1208.45000
Vampire vampire_4.8_smt_pre_vampire_smtcomp unknown ❌ 1200.03000 4766.97000
YicesQS yicesQS-2022-07-02-optim-under10_default sat ✅ 0.13753 0.13756
Z3 z3-4.8.11_default sat ✅ 0.09039 0.09030
SMT-COMP 2024 0.20 (4/5) Amaya Amaya sat ✅ 1.81071 1.70929
cvc5 cvc5 sat ✅ 0.25767 0.15805
iProver iProver v3.9 unknown ❌ 1201.74380 4770.10530
SMTInterpol SMTInterpol sat ✅ 0.60402 1.00598
YicesQS YicesQS sat ✅ 0.33659 0.21326
SMT-COMP 2025 0.25 (6/8) Amaya Amaya unsat ✅ 1.52622 1.39582
cvc5 cvc5 sat ✅ 0.30424 0.18032
iProver iProver v3.9.3 unknown ❌ 1201.79443 4787.45275
SMTInterpol SMTInterpol sat ✅ 0.56275 0.85660
UltimateEliminator UltimateEliminator+MathSAT unknown ❌ 1201.79331 1206.88508
YicesQS YicesQS sat ✅ 0.35384 0.23649
Z3alpha Z3-alpha sat ✅ 0.40105 0.28512
Z3 Z3-alpha-base sat ✅ 0.59980 0.47755