Benchmark

non-incremental/QF_NRA/20170501-Heizmann-UltimateInvariantSynthesis/standard_copyInitSum3_ground.i_3_2_2.bpl_5.smt2

Generated by a component of the Ultimate program analysis framework [1] 
that implements a constraint-based synthesis of invariants [2].

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate to benchmarks [3] from the SV-COMP 2017 [4,5].

This script might _not_ contain all SMT commands that are used by 
Ultimate . In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/
[2] Michael Colon, Sriram Sankaranarayanan, Henny Sipma: Linear Invariant 
Generation Using Non-linear Constraint Solving. CAV 2003: 420-432
[3] https://github.com/sosy-lab/sv-benchmarks
[4] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[5] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size33526
Compressed Size3159
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status unsat
Size 33518
Compressed Size3169
Max. Term Depth7
Asserts 9
Declared Functions0
Declared Constants202
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

or26 and9 =55 +354
-156 *642 <26 <=26
>26 >=178

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 1.00 (0/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.01600 598.59400
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.02700 599.95500
veriT veriT+raSAT+Redlog default unknown ❌ 600.02800 749.11000
Yices2 Yices2-Main default unknown ❌ 600.03600 599.97500
Z3 z3-4.5.0 default unknown ❌ 600.10500 599.94000
SMT-COMP 2018 0.80 (1/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.01000 1185.86000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.02000 1199.78000
SMTRAT-MCSAT-final_default unknown ❌ 1200.02000 1199.81000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.02000 1199.92000
Yices2 Yices 2.6.0_default unsat ✅ 780.39800 780.38500
Z3 z3-4.7.1_default unknown ❌ 1200.09000 1200.07000
SMT-COMP 2021 1.00 (0/10) MathSAT mathsat-5.6.6_default unknown ❌ 1200.11000 1199.84000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.10000 3558.40000
SMT-RAT smtrat-MCSAT_default unknown ❌ 1200.08000 1200.01000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.02000 1199.97000
Z3 z3-4.8.11_default unknown ❌ 1200.02000 1199.90000
SMT-COMP 2022 0.78 (2/9) cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq unknown ❌ 1200.09000 1199.99000
MathSAT MathSAT-5.6.8_default unknown ❌ 1200.05000 1199.86000
NRA-LS NRA-LS-FINAL_default unknown ❌ 1170.47000 1169.99000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.12000 3585.62000
SMT-RAT SMT-RAT-MCSAT_default unsat ✅ 671.71600 671.63900
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.03000 1200.06000
Yices2 Yices 2.6.2 for SMTCOMP 2021_default unknown ❌ 1200.02000 1199.90000
Z3 z3-4.8.17_default unknown ❌ 1200.03000 1199.82000
Z3++ z3++0715_default unsat ✅ 73.22940 73.22060