Benchmark

non-incremental/QF_NRA/20170501-Heizmann-UltimateInvariantSynthesis/standard_two_index_01.i_3_2_2.bpl_5.smt2

Generated by a component of the Ultimate program analysis framework [1] 
that implements a constraint-based synthesis of invariants [2].

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate to benchmarks [3] from the SV-COMP 2017 [4,5].

This script might _not_ contain all SMT commands that are used by 
Ultimate . In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/
[2] Michael Colon, Sriram Sankaranarayanan, Henny Sipma: Linear Invariant 
Generation Using Non-linear Constraint Solving. CAV 2003: 420-432
[3] https://github.com/sosy-lab/sv-benchmarks
[4] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[5] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size13321
Compressed Size1821
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status None
Size 13313
Compressed Size1808
Max. Term Depth7
Asserts 3
Declared Functions0
Declared Constants77
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

or8 and3 =34 +118
-71 *215 <8 <=8
>8 >=68

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 1.00 (0/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.02100 599.47000
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.01300 599.96800
veriT veriT+raSAT+Redlog default unknown ❌ 600.11700 638.09000
Yices2 Yices2-Main default unknown ❌ 600.01400 600.02000
Z3 z3-4.5.0 default unknown ❌ 600.02100 599.91000
SMT-COMP 2018 1.00 (0/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.02000 1198.07000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.05000 1200.01000
SMTRAT-MCSAT-final_default unknown ❌ 1200.06000 1200.08000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.08000 1199.94000
Yices2 Yices 2.6.0_default unknown ❌ 1200.01000 1199.93000
Z3 z3-4.7.1_default unknown ❌ 1200.10000 1199.96000
SMT-COMP 2021 1.00 (0/10) MathSAT mathsat-5.6.6_default unknown ❌ 1200.03000 1199.82000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.05000 3596.86000
SMT-RAT smtrat-MCSAT_default unknown ❌ 1200.04000 1200.07000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.03000 1199.96000
Z3 z3-4.8.11_default unknown ❌ 1200.05000 1199.77000
SMT-COMP 2023 1.00 (0/7) cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.02000 1197.50000
NRA-LS cvc5-NRA-LS-sq_default unknown ❌ 1176.35000 1170.50000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.05000 3597.81000
SMT-RAT SMT-RAT-MCSAT_default unknown ❌ 1200.01000 1199.87000
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.01000 1199.84000
Z3alpha z3alpha_default unknown ❌ 1200.02000 1199.95000
Z3++ z3++0715_default unknown ❌ 1200.11000 1200.08000
Z3++_sq_0526_default unknown ❌ 1200.02000 1199.82000
SMT-COMP 2025 1.00 (0/6) cvc5 cvc5 unknown ❌ 1201.78642 1200.97596
SMTInterpol SMTInterpol unknown ❌ 0.52150 0.68026
SMT-RAT SMT-RAT unknown ❌ 1201.31462 1201.00514
Yices2 Yices2 unknown ❌ 1201.32326 1201.10535
Z3alpha Z3-alpha unknown ❌ 1201.00595 4802.14443
Z3 Z3-alpha-base unknown ❌ 1201.30998 1201.00572
z3siri-base unknown ❌ 1201.33362 1201.04754