Benchmark

non-incremental/QF_NRA/20170501-Heizmann-UltimateInvariantSynthesis/standard_init9_ground.i_3_2_2.bpl_3.smt2

Generated by a component of the Ultimate program analysis framework [1] 
that implements a constraint-based synthesis of invariants [2].

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate to benchmarks [3] from the SV-COMP 2017 [4,5].

This script might _not_ contain all SMT commands that are used by 
Ultimate . In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/
[2] Michael Colon, Sriram Sankaranarayanan, Henny Sipma: Linear Invariant 
Generation Using Non-linear Constraint Solving. CAV 2003: 420-432
[3] https://github.com/sosy-lab/sv-benchmarks
[4] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[5] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size42512
Compressed Size4012
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status unsat
Size 42504
Compressed Size4024
Max. Term Depth7
Asserts 19
Declared Functions0
Declared Constants266
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

or38 and19 =80 +438
-227 *769 <38 <=38
>38 >=230

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 0.80 (1/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.10100 598.22300
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.07900 600.06700
veriT veriT+raSAT+Redlog default unknown ❌ 600.02700 749.76000
Yices2 Yices2-Main default unsat ✅ 201.95200 201.92000
Z3 z3-4.5.0 default unknown ❌ 600.10700 599.84000
SMT-COMP 2018 0.80 (1/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.02000 1197.65000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.08000 1200.12000
SMTRAT-MCSAT-final_default unknown ❌ 1200.05000 1200.02000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.11000 1199.90000
Yices2 Yices 2.6.0_default unsat ✅ 60.56720 60.56400
Z3 z3-4.7.1_default unknown ❌ 1200.11000 1200.03000
SMT-COMP 2020 1.00 (0/7) CVC4 CVC4-sq-final_default unknown ❌ 1200.11000 1193.11000
MathSAT MathSAT5_default.sh unknown ❌ 1200.02000 1199.51000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.14000 3594.63000
SMT-RAT smtrat-CDCAC_default unknown ❌ 1200.07000 1199.88000
smtrat-MCSAT_default unknown ❌ 1200.04000 1200.02000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.10000 1200.03000
Yices2 Yices 2.6.2 bug fix_default unknown ❌ 1200.07000 1199.88000
Z3 z3-4.8.8_default unknown ❌ 1200.01000 1199.82000
SMT-COMP 2024 0.60 (2/5) cvc5 cvc5 unknown ❌ 1201.71815 1201.05203
SMTInterpol SMTInterpol unknown ❌ 0.70982 1.41198
SMT-RAT SMT-RAT unsat ✅ 25.83645 25.73558
Yices2 Yices2 unsat ✅ 4.64570 4.54553
Z3alpha Z3-alpha unknown ❌ 1201.74458 1200.93323
SMT-COMP 2025 0.50 (3/6) cvc5 cvc5 unknown ❌ 1201.79098 1201.03045
SMTInterpol SMTInterpol unknown ❌ 0.62370 1.19127
SMT-RAT SMT-RAT unknown ❌ 1201.39843 1201.12893
Yices2 Yices2 unsat ✅ 6.61545 6.48148
Z3alpha Z3-alpha unsat ✅ 101.46445 373.25508
Z3 Z3-alpha-base unsat ✅ 32.47840 32.34320
z3siri-base unsat ✅ 32.45159 32.32759