Benchmark

non-incremental/QF_NRA/20170501-Heizmann-UltimateInvariantSynthesis/array_single_elem_init.i_4_2_2.bpl_5.smt2

Generated by a component of the Ultimate program analysis framework [1] 
that implements a constraint-based synthesis of invariants [2].

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate to benchmarks [3] from the SV-COMP 2017 [4,5].

This script might _not_ contain all SMT commands that are used by 
Ultimate . In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/
[2] Michael Colon, Sriram Sankaranarayanan, Henny Sipma: Linear Invariant 
Generation Using Non-linear Constraint Solving. CAV 2003: 420-432
[3] https://github.com/sosy-lab/sv-benchmarks
[4] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[5] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size45405
Compressed Size3879
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status None
Size 45397
Compressed Size3891
Max. Term Depth7
Asserts 5
Declared Functions0
Declared Constants195
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

or20 and5 =108 +439
-210 *826 <20 <=20
>20 >=171

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 1.00 (0/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.01400 598.60000
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.01000 599.99500
veriT veriT+raSAT+Redlog default unknown ❌ 600.04000 658.09000
Yices2 Yices2-Main default unknown ❌ 600.10300 600.06000
Z3 z3-4.5.0 default unknown ❌ 600.01300 599.78000
SMT-COMP 2018 1.00 (0/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.11000 1197.97000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.02000 1199.94000
SMTRAT-MCSAT-final_default unknown ❌ 1200.09000 1200.07000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.01000 1199.82000
Yices2 Yices 2.6.0_default unknown ❌ 1200.10000 1199.95000
Z3 z3-4.7.1_default unknown ❌ 1200.02000 1199.95000
SMT-COMP 2022 1.00 (0/9) cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq unknown ❌ 1200.02000 1198.16000
MathSAT MathSAT-5.6.8_default unknown ❌ 1200.02000 1199.87000
NRA-LS NRA-LS-FINAL_default unknown ❌ 1170.04000 1169.95000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.10000 3550.03000
SMT-RAT SMT-RAT-MCSAT_default unknown ❌ 1200.01000 1199.96000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.02000 1199.83000
Yices2 Yices 2.6.2 for SMTCOMP 2021_default unknown ❌ 1200.10000 1200.03000
Z3 z3-4.8.17_default unknown ❌ 1200.02000 1199.84000
Z3++ z3++0715_default unknown ❌ 1200.11000 1200.00000
SMT-COMP 2023 1.00 (0/7) cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.10000 1197.37000
NRA-LS cvc5-NRA-LS-sq_default unknown ❌ 1175.26000 1170.62000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.06000 3597.56000
SMT-RAT SMT-RAT-MCSAT_default unknown ❌ 1200.02000 1200.05000
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.10000 1199.88000
Z3alpha z3alpha_default unknown ❌ 1200.12000 1200.08000
Z3++ z3++0715_default unknown ❌ 1200.02000 1199.97000
Z3++_sq_0526_default unknown ❌ 1200.03000 1199.83000
SMT-COMP 2024 1.00 (0/5) cvc5 cvc5 unknown ❌ 1201.72005 1200.71158
SMTInterpol SMTInterpol unknown ❌ 0.68411 1.35594
SMT-RAT SMT-RAT unknown ❌ 1201.74509 1201.11646
Yices2 Yices2 unknown ❌ 1201.25623 1200.80525
Z3alpha Z3-alpha unknown ❌ 1201.74975 1200.85043