Benchmark

non-incremental/QF_NRA/20170501-Heizmann-UltimateInvariantSynthesis/cggmp2005_variant.c.i_3_3_2.bpl_5.smt2

Generated by a component of the Ultimate program analysis framework [1] 
that implements a constraint-based synthesis of invariants [2].

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate to benchmarks [3] from the SV-COMP 2017 [4,5].

This script might _not_ contain all SMT commands that are used by 
Ultimate . In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/
[2] Michael Colon, Sriram Sankaranarayanan, Henny Sipma: Linear Invariant 
Generation Using Non-linear Constraint Solving. CAV 2003: 420-432
[3] https://github.com/sosy-lab/sv-benchmarks
[4] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[5] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size15733
Compressed Size1993
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status None
Size 15725
Compressed Size1983
Max. Term Depth7
Asserts 3
Declared Functions0
Declared Constants84
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

or8 and3 =37 +152
-98 *281 <8 <=8
>8 >=72

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 1.00 (0/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.11600 599.21000
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.06700 600.08700
veriT veriT+raSAT+Redlog default unknown ❌ 600.02200 713.17000
Yices2 Yices2-Main default unknown ❌ 600.02100 599.92000
Z3 z3-4.5.0 default unknown ❌ 600.02800 599.89000
SMT-COMP 2018 1.00 (0/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.02000 1198.99000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.01000 1199.73000
SMTRAT-MCSAT-final_default unknown ❌ 1200.01000 1199.93000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.02000 1199.87000
Yices2 Yices 2.6.0_default unknown ❌ 1200.01000 1199.85000
Z3 z3-4.7.1_default unknown ❌ 1200.02000 1199.79000
SMT-COMP 2024 0.80 (1/5) cvc5 cvc5 unknown ❌ 1201.71616 1200.73785
SMTInterpol SMTInterpol unknown ❌ 0.51682 0.82863
SMT-RAT SMT-RAT sat ✅ 26.11641 26.01603
Yices2 Yices2 unknown ❌ 1201.24508 1200.90392
Z3alpha Z3-alpha unknown ❌ 1201.71336 1200.67338
SMT-COMP 2025 1.00 (0/6) cvc5 cvc5 unknown ❌ 1201.78755 1201.01957
SMTInterpol SMTInterpol unknown ❌ 0.53757 0.77437
SMT-RAT SMT-RAT unknown ❌ 1201.28774 1201.03331
Yices2 Yices2 unknown ❌ 1201.28777 1201.03421
Z3alpha Z3-alpha unknown ❌ 1201.00565 4802.14934
Z3 Z3-alpha-base unknown ❌ 1201.26544 1200.97548
z3siri-base unknown ❌ 1201.26623 1201.05379