Benchmark
non-incremental/QF_NRA/hycomp/ball_count_1d_plain.10.redlog_global_14.smt2
Benchmarks generated from hycomp (https://es-static.fbk.eu/tools/hycomp/). BMC instances of non-linear hybrid automata taken from: Alessandro Cimatti, Sergio Mover, Stefano Tonetta, A quantifier-free SMT encoding of non-linear hybrid automata, FMCAD 2012 and Alessandro Cimatti, Sergio Mover, Stefano Tonetta, Quantier-free encoding of invariants for Hybrid Systems, Formal Methods in System Design. This instance solves a BMC problem of depth 14 and uses the encoding obtained with quantifier elimination using redlog encoding. Contacts: Sergio Mover (mover@fbk.eu), Stefano Tonetta (tonettas@fbk.eu), Alessandro Cimatti (cimatti@fbk.eu).
| Benchmark |
|---|
| Size | 119858 |
| Compressed Size | 21812 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2014-07-21 |
| Generated By | — |
| Generated On | — |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unsat |
| Inferred Status | unsat |
| Size | 119850 |
| Compressed Size | 21852 |
| Max. Term Depth | 2524 |
| Asserts | 1 |
| Declared Functions | 0 |
| Declared Constants | 166 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
not | 238 |
or | 676 |
and | 792 |
= | 228 |
let | 2521 |
/ | 2 |
+ | 159 |
- | 101 |
* | 277 |
<= | 151 |
| | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2014
|
0.25 (3/4) |
CVC3 |
CVC3 default |
unsat ✅
|
5.79066
|
5.78512
|
| |
CVC4 |
CVC4 f7118b2 default |
unsat ✅
|
0.10203
|
0.09098
|
| |
raSAT |
raSAT-main-track-final default.sh |
unknown ❌
|
0.01864
|
0.00500
|
| |
Z3 |
Z3-4.3.2.a054b099c1d6-x64-debian-6.0.6-SMT-COMP-2014 default |
unsat ✅
|
16.13520
|
16.13350
|
|
SMT-COMP 2015
|
0.33 (4/6) |
CVC3 |
CVC3 default |
unsat ✅
|
5.08587
|
5.08723
|
| |
CVC4 |
CVC4-master-2015-06-15-9b32405-main default |
unsat ✅
|
0.10524
|
0.10298
|
| |
|
CVC4-experimental-2015-06-15-ff5745a-main default |
unsat ✅
|
0.10082
|
0.09898
|
| |
raSAT |
raSAT default.sh |
unknown ❌
|
2400.02000
|
2400.70000
|
| |
SMT-RAT |
SMT-RAT-final default |
unknown ❌
|
2400.01000
|
2401.10000
|
| |
Yices2 |
Yices2-NL default |
unsat ✅
|
0.01762
|
0.01700
|
| |
Z3 |
z3 4.4.0 default |
unsat ✅
|
15.48900
|
15.49660
|
|
SMT-COMP 2016
|
0.20 (4/5) |
CVC4 |
CVC4-master-2016-05-27-cfef263-main default |
unsat ✅
|
0.10116
|
0.10134
|
| |
raSAT |
raSAT 0.3 default.sh |
unsat ✅
|
0.97003
|
0.96247
|
| |
|
raSAT 0.4 exp - final default.py |
unsat ✅
|
0.99402
|
1.91000
|
| |
SMT-RAT |
SMT-RAT default |
unknown ❌
|
2400.05000
|
2401.44000
|
| |
Yices2 |
Yices-2.4.2 default |
unsat ✅
|
0.01798
|
0.01795
|
| |
Z3 |
z3-4.4.1 default |
unsat ✅
|
15.47830
|
15.48790
|
|
SMT-COMP 2017
|
0.20 (4/5) |
CVC4 |
CVC4-smtcomp2017-main default |
unsat ✅
|
0.10902
|
0.10840
|
| |
SMT-RAT |
SMTRAT-comp2017_2 default |
unknown ❌
|
600.06200
|
600.04200
|
| |
veriT |
veriT+raSAT+Redlog default |
unsat ✅
|
0.03213
|
0.03098
|
| |
Yices2 |
Yices2-Main default |
unsat ✅
|
0.01830
|
0.01757
|
| |
Z3 |
z3-4.5.0 default |
unsat ✅
|
15.53240
|
15.52680
|
|
SMT-COMP 2018
|
0.20 (4/5) |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
unsat ✅
|
0.11393
|
0.11414
|
| |
SMT-RAT |
SMTRAT-Rat-final_default |
unknown ❌
|
1200.10000
|
1199.94000
|
| |
|
SMTRAT-MCSAT-final_default |
unknown ❌
|
1200.05000
|
1199.90000
|
| |
veriT |
veriT+raSAT+Reduce_default |
unsat ✅
|
0.02940
|
0.02931
|
| |
Yices2 |
Yices 2.6.0_default |
unsat ✅
|
0.01890
|
0.01884
|
| |
Z3 |
z3-4.7.1_default |
unsat ✅
|
15.11130
|
15.10980
|
|
SMT-COMP 2020
|
0.14 (6/7) |
CVC4 |
CVC4-sq-final_default |
unsat ✅
|
0.15885
|
0.15902
|
| |
MathSAT |
MathSAT5_default.sh |
unsat ✅
|
0.04223
|
0.04215
|
| |
Par4 |
Par4-wrapped-sq_default |
unsat ✅
|
0.02885
|
0.00641
|
| |
SMT-RAT |
smtrat-CDCAC_default |
unknown ❌
|
1200.01000
|
1199.86000
|
| |
|
smtrat-MCSAT_default |
unknown ❌
|
1200.04000
|
1199.91000
|
| |
veriT |
veriT+raSAT+Redlog_default |
unsat ✅
|
0.03180
|
0.03176
|
| |
Yices2 |
Yices 2.6.2 bug fix_default |
unsat ✅
|
0.03102
|
0.03096
|
| |
Z3 |
z3-4.8.8_default |
unsat ✅
|
15.06950
|
15.06940
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
unsat ✅
|
0.26804
|
0.16809
|
| |
SMTInterpol |
SMTInterpol |
unsat ✅
|
1.22984
|
3.30333
|
| |
SMT-RAT |
SMT-RAT |
unsat ✅
|
1.48375
|
1.38375
|
| |
Yices2 |
Yices2 |
unsat ✅
|
0.23107
|
0.13126
|
| |
Z3alpha |
Z3-alpha |
unsat ✅
|
15.29754
|
15.19728
|