Benchmark
non-incremental/QF_NRA/hycomp/etcs_braking_2.01.redlog_global_10.smt2
Benchmarks generated from hycomp (https://es-static.fbk.eu/tools/hycomp/). BMC instances of non-linear hybrid automata taken from: Alessandro Cimatti, Sergio Mover, Stefano Tonetta, A quantifier-free SMT encoding of non-linear hybrid automata, FMCAD 2012 and Alessandro Cimatti, Sergio Mover, Stefano Tonetta, Quantier-free encoding of invariants for Hybrid Systems, Formal Methods in System Design. This instance solves a BMC problem of depth 10 and uses the encoding obtained with quantifier elimination using redlog encoding. Contacts: Sergio Mover (mover@fbk.eu), Stefano Tonetta (tonettas@fbk.eu), Alessandro Cimatti (cimatti@fbk.eu).
| Benchmark |
|---|
| Size | 282714 |
| Compressed Size | 50672 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2014-07-21 |
| Generated By | — |
| Generated On | — |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unsat |
| Inferred Status | unsat |
| Size | 282706 |
| Compressed Size | 50680 |
| Max. Term Depth | 5788 |
| Asserts | 1 |
| Declared Functions | 0 |
| Declared Constants | 240 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
not | 481 |
or | 1072 |
and | 1518 |
= | 500 |
let | 5785 |
/ | 108 |
+ | 565 |
- | 383 |
* | 902 |
<= | 747 |
| | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2014
|
0.50 (2/4) |
CVC3 |
CVC3 default |
unknown ❌
|
2404.55000
|
2402.35000
|
| |
CVC4 |
CVC4 f7118b2 default |
unsat ✅
|
0.27277
|
0.26196
|
| |
raSAT |
raSAT-main-track-final default.sh |
unknown ❌
|
0.01955
|
0.00700
|
| |
Z3 |
Z3-4.3.2.a054b099c1d6-x64-debian-6.0.6-SMT-COMP-2014 default |
unsat ✅
|
31.76940
|
31.76920
|
|
SMT-COMP 2015
|
0.17 (5/6) |
CVC3 |
CVC3 default |
unsat ✅
|
1.86723
|
1.86771
|
| |
CVC4 |
CVC4-master-2015-06-15-9b32405-main default |
unsat ✅
|
0.29120
|
0.28796
|
| |
|
CVC4-experimental-2015-06-15-ff5745a-main default |
unsat ✅
|
0.29071
|
0.28896
|
| |
raSAT |
raSAT default.sh |
unsat ✅
|
2400.01000
|
2400.74000
|
| |
SMT-RAT |
SMT-RAT-final default |
unknown ❌
|
2400.01000
|
2400.41000
|
| |
Yices2 |
Yices2-NL default |
unsat ✅
|
1.75247
|
1.75173
|
| |
Z3 |
z3 4.4.0 default |
unsat ✅
|
19.88480
|
19.89300
|
|
SMT-COMP 2016
|
0.40 (3/5) |
CVC4 |
CVC4-master-2016-05-27-cfef263-main default |
unsat ✅
|
0.27745
|
0.27779
|
| |
raSAT |
raSAT 0.3 default.sh |
unknown ❌
|
2400.03000
|
2401.24000
|
| |
|
raSAT 0.4 exp - final default.py |
unknown ❌
|
2400.03000
|
4816.74000
|
| |
SMT-RAT |
SMT-RAT default |
unknown ❌
|
2400.05000
|
2401.27000
|
| |
Yices2 |
Yices-2.4.2 default |
unsat ✅
|
0.53828
|
0.53855
|
| |
Z3 |
z3-4.4.1 default |
unsat ✅
|
20.55010
|
20.56350
|
|
SMT-COMP 2017
|
0.20 (4/5) |
CVC4 |
CVC4-smtcomp2017-main default |
unsat ✅
|
0.28149
|
0.28096
|
| |
SMT-RAT |
SMTRAT-comp2017_2 default |
unknown ❌
|
600.07400
|
599.98000
|
| |
veriT |
veriT+raSAT+Redlog default |
unsat ✅
|
0.06234
|
0.06191
|
| |
Yices2 |
Yices2-Main default |
unsat ✅
|
0.33331
|
0.33266
|
| |
Z3 |
z3-4.5.0 default |
unsat ✅
|
20.83960
|
20.83580
|
|
SMT-COMP 2018
|
0.20 (4/5) |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
unsat ✅
|
0.33243
|
0.33264
|
| |
SMT-RAT |
SMTRAT-Rat-final_default |
unknown ❌
|
1200.01000
|
1199.89000
|
| |
|
SMTRAT-MCSAT-final_default |
unknown ❌
|
1200.02000
|
1199.51000
|
| |
veriT |
veriT+raSAT+Reduce_default |
unsat ✅
|
0.06076
|
0.06069
|
| |
Yices2 |
Yices 2.6.0_default |
unsat ✅
|
0.20606
|
0.20600
|
| |
Z3 |
z3-4.7.1_default |
unsat ✅
|
15.49150
|
15.48990
|
|
SMT-COMP 2020
|
|
CVC4 |
CVC4-sq-final_default |
unsat ✅
|
0.44708
|
0.44732
|
| |
MathSAT |
MathSAT5_default.sh |
unsat ✅
|
0.10142
|
0.10138
|
| |
Par4 |
Par4-wrapped-sq_default |
unsat ✅
|
0.21134
|
0.01005
|
| |
SMT-RAT |
smtrat-CDCAC_default |
unknown ❌
|
1200.09000
|
1199.17000
|
| |
|
smtrat-MCSAT_default |
unsat ✅
|
22.83690
|
22.83310
|
| |
veriT |
veriT+raSAT+Redlog_default |
unsat ✅
|
0.06550
|
0.06542
|
| |
Yices2 |
Yices 2.6.2 bug fix_default |
unsat ✅
|
0.32283
|
0.32277
|
| |
Z3 |
z3-4.8.8_default |
unsat ✅
|
15.20730
|
15.20550
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
unsat ✅
|
0.34770
|
0.24781
|
| |
SMTInterpol |
SMTInterpol |
unsat ✅
|
1.82602
|
5.32052
|
| |
SMT-RAT |
SMT-RAT |
unsat ✅
|
12.39507
|
12.29512
|
| |
Yices2 |
Yices2 |
unsat ✅
|
0.30530
|
0.20571
|
| |
Z3alpha |
Z3-alpha |
unsat ✅
|
15.41494
|
15.31525
|