Benchmark

non-incremental/QF_NRA/hycomp/ball_count_2d_hill.03.redlog_global_10.smt2

Benchmarks generated from hycomp (https://es-static.fbk.eu/tools/hycomp/). BMC instances of non-linear hybrid automata taken from: Alessandro Cimatti, Sergio Mover, Stefano Tonetta, A quantifier-free SMT encoding of non-linear hybrid automata, FMCAD 2012 and Alessandro Cimatti, Sergio Mover, Stefano Tonetta, Quantier-free encoding of invariants for Hybrid Systems, Formal Methods in System Design. This instance solves a BMC problem of depth 10 and uses the encoding obtained with quantifier elimination using redlog encoding. Contacts: Sergio Mover (mover@fbk.eu), Stefano Tonetta (tonettas@fbk.eu), Alessandro Cimatti (cimatti@fbk.eu).
Benchmark
Size204308
Compressed Size38186
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2014-07-21
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status None
Size 204300
Compressed Size37752
Max. Term Depth4463
Asserts 1
Declared Functions0
Declared Constants155
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

not218 or576 and791 =270
let4460 /2 +777 -293
*1618 <=210

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 1.00 (0/5) CVC4 CVC4-smtcomp2017-main default unknown ❌ 600.02000 598.73100
SMT-RAT SMTRAT-comp2017_2 default unknown ❌ 600.03700 599.96000
veriT veriT+raSAT+Redlog default unknown ❌ 600.02800 635.52000
Yices2 Yices2-Main default unknown ❌ 600.10600 600.08000
Z3 z3-4.5.0 default unknown ❌ 600.04900 600.05000
SMT-COMP 2018 1.00 (0/5) CVC4 master-2018-06-10-b19c840-competition-default_default unknown ❌ 1200.11000 1198.27000
SMT-RAT SMTRAT-Rat-final_default unknown ❌ 1200.02000 1199.83000
SMTRAT-MCSAT-final_default unknown ❌ 1200.02000 1199.93000
veriT veriT+raSAT+Reduce_default unknown ❌ 1200.02000 1199.75000
Yices2 Yices 2.6.0_default unknown ❌ 1200.10000 1199.97000
Z3 z3-4.7.1_default unknown ❌ 1200.09000 1200.08000
SMT-COMP 2019 1.00 (0/7) CVC4 CVC4-2019-06-03-d350fe1-wrapped-sq_default unknown ❌ 2400.10000 2396.83000
CVC4-SymBreak_03_06_2019-wrapped-sq_default unknown ❌ 2400.06000 2392.21000
MathSAT mathsat-20190601-wrapped-sq_default unknown ❌ 2400.02000 2399.61000
mathsat-na-20190601-wrapped-sq_default unknown ❌ 2400.11000 2400.12000
Par4 Par4-wrapped-sq_default unknown ❌ 2400.06000 7196.86000
SMT-RAT SMTRAT-5-wrapped-sq_default unknown ❌ 2400.06000 2399.54000
SMTRAT-MCSAT-4-wrapped-sq_default unknown ❌ 2400.02000 2399.83000
veriT veriT+raSAT+Redlog-wrapped-sq_default unknown ❌ 2400.02000 2401.98000
Yices2 Yices 2.6.2-wrapped-sq_default unknown ❌ 2400.04000 2399.97000
Z3 z3-4.8.4-d6df51951f4c-wrapped-sq_default unknown ❌ 2400.06000 2400.07000
z3-4.7.1_default unknown ❌ 2400.09000 2399.94000
SMT-COMP 2020 1.00 (0/7) CVC4 CVC4-sq-final_default unknown ❌ 1200.02000 1196.95000
MathSAT MathSAT5_default.sh unknown ❌ 1200.11000 1200.04000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.06000 3597.49000
SMT-RAT smtrat-CDCAC_default unknown ❌ 1200.02000 1199.89000
smtrat-MCSAT_default unknown ❌ 1200.01000 1199.86000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.09000 1200.03000
Yices2 Yices 2.6.2 bug fix_default unknown ❌ 1200.02000 1199.74000
Z3 z3-4.8.8_default unknown ❌ 1200.02000 1199.90000
SMT-COMP 2021 1.00 (0/10) MathSAT mathsat-5.6.6_default unknown ❌ 1200.02000 1199.83000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.15000 3596.54000
SMT-RAT smtrat-MCSAT_default unknown ❌ 443.60400 443.50200
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.11000 1201.76000
Z3 z3-4.8.11_default unknown ❌ 1200.11000 1199.97000
SMT-COMP 2022 1.00 (0/9) cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq unknown ❌ 1200.10000 1199.72000
MathSAT MathSAT-5.6.8_default unknown ❌ 1200.02000 1200.02000
NRA-LS NRA-LS-FINAL_default unknown ❌ 1170.10000 1170.03000
Par4 Par4-wrapped-sq_default unknown ❌ 1200.13000 2748.12000
SMT-RAT SMT-RAT-MCSAT_default unknown ❌ 1200.11000 1199.98000
veriT veriT+raSAT+Redlog_default unknown ❌ 1200.03000 1489.31000
Yices2 Yices 2.6.2 for SMTCOMP 2021_default unknown ❌ 1200.06000 1199.88000
Z3 z3-4.8.17_default unknown ❌ 1200.11000 1200.05000
Z3++ z3++0715_default unknown ❌ 1200.03000 1199.64000
SMT-COMP 2025 1.00 (0/6) cvc5 cvc5 unknown ❌ 1201.78761 1201.03732
SMTInterpol SMTInterpol unknown ❌ 1.09744 2.78541
SMT-RAT SMT-RAT unknown ❌ 1201.42207 1201.16454
Yices2 Yices2 unknown ❌ 1201.30385 1201.04172
Z3alpha Z3-alpha unknown ❌ 1201.00508 4801.18679
Z3 Z3-alpha-base unknown ❌ 1201.43721 1201.15102
z3siri-base unknown ❌ 1201.44203 1201.16267