Benchmark
non-incremental/QF_BV/20230221-oisc-gurtner/AND-NESTED-8-32-src-sp-not-excluded.smt2
Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)
The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.
There are two parameters in the translation:
- the bitwidth we are considering
- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)
One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.
Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
| Benchmark |
|---|
| Size | 21640223 |
| Compressed Size | 2172860 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2023-07-06 |
| Generated By | Sonja Gurtner and Mathias Fleury |
| Generated On | 2023-02-19 00:00:00 |
| Generator | Rosette |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 21640214 |
| Compressed Size | 2172844 |
| Max. Term Depth | 3 |
| Asserts | 2 |
| Declared Functions | 0 |
| Declared Constants | 139 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 302089 |
| Declared Datatypes | 0 |
Symbols
Bool | 37590 |
ite | 357443 |
not | 5019 |
or | 11214 |
and | 17673 |
= | 3645 |
BitVec | 264499 |
bvand | 1 |
bvor | 2806 |
bvneg | 2629 |
bvadd | 2529 |
bvsmod | 2 |
bvult | 26 |
bvule | 4 |
bvslt | 1 |
bvsle | 8 |
bvlshr | 43 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2023
|
0.67 (2/6) |
Bitwuzla |
Bitwuzla-fixed_default |
sat ✅
|
306.96200
|
306.95700
|
| |
cvc5 |
cvc5-default-2023-05-16-ea045f305_sq |
unknown ❌
|
1200.03000
|
1199.81000
|
| |
STP |
STP 2022.4_default |
sat ✅
|
647.48700
|
647.36500
|
| |
|
STP 2022.4_default |
sat ✅
|
650.93800
|
650.94600
|
| |
UltimateEliminator |
UltimateIntBlastingWrapper+SMTInterpol_default |
unknown ❌
|
4.79143
|
13.44500
|
| |
Yices2 |
Yices 2 for SMTCOMP 2023_default |
unknown ❌
|
1200.02000
|
1199.95000
|
| |
Z3-Owl |
z3-Owl-Final_default |
unknown ❌
|
1200.10000
|
1199.76000
|
| |
|
z3-Owl-Final_default |
unknown ❌
|
1200.04000
|
1199.42000
|