Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRLI-SAFE-1024-1024.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size1770767
Compressed Size268747
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status None
Size 1770758
Compressed Size268756
Max. Term Depth3
Asserts 3
Declared Functions0
Declared Constants139
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants33988
Declared Datatypes0

Symbols

Bool18264 ite5714 not4112 or5144
and5312 =3673 BitVec15724 bvand1
bvor8 bvneg1039 bvadd3087 bvsmod2
bvult9 bvule4 bvslt1 bvsle9
bvshl4092 bvlshr1036

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 1.00 (0/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.02000 1199.67000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 565.61800 565.47500
STP STP 2022.4_default unknown ❌ 1200.03000 1199.73000
STP 2022.4_default unknown ❌ 1200.03000 1199.82000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 11.08750 24.38330
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.03000 1199.85000
Z3-Owl z3-Owl-Final_default unknown ❌ 1200.02000 1199.84000
z3-Owl-Final_default unknown ❌ 1200.04000 1199.96000
SMT-COMP 2024 1.00 (0/6) Bitwuzla Bitwuzla unknown ❌ 1201.44407 1200.86733
cvc5 cvc5 unknown ❌ 176.20546 177.86067
SMTInterpol SMTInterpol unknown ❌ 1202.74619 1376.43717
STP STP unknown ❌ 1201.40142 1201.27087
Yices2 Yices2 unknown ❌ 1201.41684 1200.80508
Z3alpha Z3-alpha unknown ❌ 418.71650 418.59262
SMT-COMP 2025 1.00 (0/9) Bitwuzla Bitwuzla unknown ❌ 1201.34720 1201.08645
Bitwuzla-MachBV-base unknown ❌ 1201.51026 1201.16445
Bitwuzla-MachBV Bitwuzla-MachBV unknown ❌ 1201.38321 1201.05190
BVDecide bv_decide unknown ❌ 1201.41379 1201.09805
bv_decide-nokernel unknown ❌ 1201.35153 1200.88972
cvc5 cvc5 unknown ❌ 151.92765 153.81154
SMTInterpol SMTInterpol unknown ❌ 1201.76817 1459.95581
Yices2 Yices2 unknown ❌ 1201.49041 1201.22357
Z3alpha Z3-alpha unknown ❌ 70.54788 278.27676
Z3 Z3-alpha-base unknown ❌ 1201.42056 1201.03722
Z3-Owl-base unknown ❌ 1201.44556 1201.12362
z3siri-base unknown ❌ 1201.46879 1201.14950
Z3-Owl Z3-Owl unknown ❌ 1201.75590 1201.25425