Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/AND-NESTED-32-32-src-sp-not-excluded.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size89310244
Compressed Size8686583
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status sat
Inferred Status None
Size 89310235
Compressed Size8686589
Max. Term Depth3
Asserts 2
Declared Functions0
Declared Constants139
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants1200433
Declared Datatypes0

Symbols

Bool145638 ite1425587 not19995 or44670
and69993 =10941 BitVec1054795 bvand1
bvor11182 bvneg10453 bvadd9969 bvsmod2
bvult26 bvule4 bvslt1 bvsle8
bvlshr91

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 1.00 (0/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.02000 1199.44000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.03000 1199.68000
STP STP 2022.4_default unknown ❌ 1200.01000 1199.77000
STP 2022.4_default unknown ❌ 1200.12000 1199.77000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.95275 13.38380
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.07000 1199.87000
Z3-Owl z3-Owl-Final_default unknown ❌ 1200.02000 1199.65000
z3-Owl-Final_default unknown ❌ 1200.09000 1199.94000
SMT-COMP 2024 1.00 (0/6) Bitwuzla Bitwuzla unknown ❌ 243.22679 244.89920
cvc5 cvc5 unknown ❌ 513.43075 514.87074
SMTInterpol SMTInterpol unknown ❌ 1202.25531 1260.88107
STP STP unknown ❌ 46.81064 46.68248
Yices2 Yices2 unknown ❌ 103.02830 104.69336
Z3alpha Z3-alpha unknown ❌ 1203.72937 1202.34508
SMT-COMP 2025 1.00 (0/9) Bitwuzla Bitwuzla unknown ❌ 162.75955 163.05834
Bitwuzla-MachBV-base unknown ❌ 269.54118 271.31033
Bitwuzla-MachBV Bitwuzla-MachBV unknown ❌ 120.95610 122.77067
BVDecide bv_decide unknown ❌ 9.08790 8.95952
bv_decide-nokernel unknown ❌ 9.14234 9.01612
cvc5 cvc5 unknown ❌ 336.12603 337.97128
SMTInterpol SMTInterpol unknown ❌ 1201.65384 1248.48600
Yices2 Yices2 unknown ❌ 102.87214 104.82836
Z3alpha Z3-alpha unknown ❌ 1202.28558 1201.50112
Z3 Z3-alpha-base unknown ❌ 93.32745 95.05561
Z3-Owl-base unknown ❌ 265.03217 266.71799
z3siri-base unknown ❌ 97.27352 99.02752
Z3-Owl Z3-Owl unknown ❌ 151.00859 150.85214