Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-112-112.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size363670
Compressed Size57344
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status unsat
Size 363661
Compressed Size57350
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants7180
Declared Datatypes0

Symbols

Bool4577 ite1411 not910 or1140
and1309 =1191 BitVec2603 bvand1
bvor9 bvneg127 bvadd572 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl556 bvlshr123 bvashr1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 0.67 (2/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.01000 1199.72000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.02000 1199.63000
STP STP 2022.4_default unsat ✅ 110.10900 110.10600
STP 2022.4_default unsat ✅ 110.22300 110.10000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.38257 22.93720
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.02000 1199.85000
Z3-Owl z3-Owl-Final_default unsat ✅ 111.38600 111.38400
z3-Owl-Final_default unsat ✅ 80.47610 80.45780
SMT-COMP 2024 0.67 (2/6) Bitwuzla Bitwuzla unsat ✅ 263.68485 263.58074
cvc5 cvc5 unknown ❌ 1201.71205 1201.14561
SMTInterpol SMTInterpol unknown ❌ 1202.74566 1737.33460
STP STP unknown ❌ 1201.23186 1201.04827
Yices2 Yices2 unsat ✅ 127.87763 127.77211
Z3alpha Z3-alpha unknown ❌ 1201.71578 1201.22854
SMT-COMP 2025 0.56 (4/9) Bitwuzla Bitwuzla unknown ❌ 1201.27046 1201.01218
Bitwuzla-MachBV-base unknown ❌ 1201.28335 1201.02858
Bitwuzla-MachBV Bitwuzla-MachBV unsat ✅ 85.74284 85.61962
BVDecide bv_decide unknown ❌ 1201.38673 1201.08030
bv_decide-nokernel unknown ❌ 1201.37125 1200.97542
cvc5 cvc5 unknown ❌ 1201.75615 1200.96802
SMTInterpol SMTInterpol unknown ❌ 1201.89348 4126.90997
Yices2 Yices2 unsat ✅ 123.18166 123.04706
Z3alpha Z3-alpha unknown ❌ 514.42968 2051.31962
Z3 Z3-alpha-base unsat ✅ 472.30213 472.12231
Z3-Owl-base unsat ✅ 1122.51520 1122.28343
z3siri-base unsat ✅ 469.76085 469.55088
Z3-Owl Z3-Owl unsat ✅ 142.48704 142.35339