Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-128-128.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size404331
Compressed Size63752
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status unsat
Size 404322
Compressed Size63740
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants8028
Declared Datatypes0

Symbols

Bool5105 ite1523 not1038 or1300
and1469 =1271 BitVec2923 bvand1
bvor9 bvneg143 bvadd652 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl636 bvlshr139 bvashr1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 0.67 (2/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.10000 1200.02000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.12000 1199.53000
STP STP 2022.4_default unsat ✅ 327.11000 327.10000
STP 2022.4_default unsat ✅ 317.76800 317.74800
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.38584 11.39790
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.02000 1200.01000
Z3-Owl z3-Owl-Final_default unsat ✅ 158.28100 158.26400
z3-Owl-Final_default unsat ✅ 100.71000 100.69900
SMT-COMP 2024 0.67 (2/6) Bitwuzla Bitwuzla unknown ❌ 1201.30311 1201.12436
cvc5 cvc5 unknown ❌ 1201.71917 1200.72162
SMTInterpol SMTInterpol unknown ❌ 1202.73091 1886.94278
STP STP unsat ✅ 558.75342 558.48625
Yices2 Yices2 unsat ✅ 208.05642 207.87330
Z3alpha Z3-alpha unknown ❌ 1201.71936 1201.29607
SMT-COMP 2025 0.56 (4/9) Bitwuzla Bitwuzla unknown ❌ 1201.29331 1200.99361
Bitwuzla-MachBV-base unknown ❌ 1201.30469 1201.06516
Bitwuzla-MachBV Bitwuzla-MachBV unsat ✅ 44.50695 44.38236
BVDecide bv_decide unknown ❌ 1201.38693 1200.97712
bv_decide-nokernel unknown ❌ 1201.38855 1201.07957
cvc5 cvc5 unknown ❌ 1201.76881 1200.99679
SMTInterpol SMTInterpol unknown ❌ 1201.89124 4120.44561
Yices2 Yices2 unsat ✅ 129.17635 129.03616
Z3alpha Z3-alpha unknown ❌ 362.72933 1444.74180
Z3 Z3-alpha-base unsat ✅ 324.65865 324.44256
Z3-Owl-base unsat ✅ 931.92278 931.67836
z3siri-base unsat ✅ 316.63328 316.47605
Z3-Owl Z3-Owl unsat ✅ 213.41036 213.26610