Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/AND-NESTED-16-32-src-sp-not-excluded.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size44213834
Compressed Size4349369
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status sat
Inferred Status None
Size 44213825
Compressed Size4349379
Max. Term Depth3
Asserts 2
Declared Functions0
Declared Constants139
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants601537
Declared Datatypes0

Symbols

Bool73606 ite713491 not10011 or22366
and35113 =6077 BitVec527931 bvand1
bvor5598 bvneg5237 bvadd5009 bvsmod2
bvult26 bvule4 bvslt1 bvsle8
bvlshr59