Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-512-512.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size1429945
Compressed Size220934
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status None
Size 1429936
Compressed Size220940
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants28380
Declared Datatypes0

Symbols

Bool17777 ite4211 not4110 or5140
and5309 =3191 BitVec10603 bvand1
bvor9 bvneg527 bvadd2572 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl2556 bvlshr523 bvashr1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 1.00 (0/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.03000 1199.90000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.02000 1199.86000
STP STP 2022.4_default unknown ❌ 1200.02000 1199.92000
STP 2022.4_default unknown ❌ 1200.02000 1199.93000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.48961 11.54470
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.11000 1199.91000
Z3-Owl z3-Owl-Final_default unknown ❌ 1200.03000 1199.81000
z3-Owl-Final_default unknown ❌ 1200.02000 1199.85000
SMT-COMP 2024 1.00 (0/6) Bitwuzla Bitwuzla unknown ❌ 1201.42680 1201.12532
cvc5 cvc5 unknown ❌ 198.52150 200.22367
SMTInterpol SMTInterpol unknown ❌ 1202.72795 1938.87557
STP STP unknown ❌ 1201.28846 1200.73740
Yices2 Yices2 unknown ❌ 1201.31846 1201.12551
Z3alpha Z3-alpha unknown ❌ 461.30260 461.18119
SMT-COMP 2025 1.00 (0/9) Bitwuzla Bitwuzla unknown ❌ 1201.40292 1201.10737
Bitwuzla-MachBV-base unknown ❌ 1201.41486 1201.17752
Bitwuzla-MachBV Bitwuzla-MachBV unknown ❌ 1201.37301 1201.08627
BVDecide bv_decide unknown ❌ 1201.38611 1201.07186
bv_decide-nokernel unknown ❌ 1201.35190 1200.94102
cvc5 cvc5 unknown ❌ 159.19373 160.96090
SMTInterpol SMTInterpol unknown ❌ 1201.75353 3712.41136
Yices2 Yices2 unknown ❌ 1201.38527 1201.12283
Z3alpha Z3-alpha unknown ❌ 122.22197 486.26637
Z3 Z3-alpha-base unknown ❌ 1201.41568 1201.11089
Z3-Owl-base unknown ❌ 1201.40079 1200.99716
z3siri-base unknown ❌ 1201.40005 1201.07249
Z3-Owl Z3-Owl unknown ❌ 1201.79494 1201.26141