Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-256-256.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size742847
Compressed Size115031
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status unsat
Size 742838
Compressed Size115038
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants14812
Declared Datatypes0

Symbols

Bool9329 ite2419 not2062 or2580
and2749 =1911 BitVec5483 bvand1
bvor9 bvneg271 bvadd1292 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl1276 bvlshr267 bvashr1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 0.83 (1/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.10000 1199.89000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.12000 1199.46000
STP STP 2022.4_default unknown ❌ 1200.09000 1200.01000
STP 2022.4_default unknown ❌ 1200.02000 1199.96000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.47559 11.34900
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.03000 1200.02000
Z3-Owl z3-Owl-Final_default unsat ✅ 884.51600 884.52600
z3-Owl-Final_default unsat ✅ 402.68100 402.63900
SMT-COMP 2024 0.83 (1/6) Bitwuzla Bitwuzla unknown ❌ 1201.32170 1200.69865
cvc5 cvc5 unknown ❌ 1201.71409 1201.06187
SMTInterpol SMTInterpol unknown ❌ 1202.75065 2239.29848
STP STP unknown ❌ 1201.27166 1200.89310
Yices2 Yices2 unsat ✅ 997.53947 997.38948
Z3alpha Z3-alpha unknown ❌ 329.18746 329.00907
SMT-COMP 2025 0.78 (2/9) Bitwuzla Bitwuzla unknown ❌ 1201.28990 1201.01078
Bitwuzla-MachBV-base unknown ❌ 1201.33891 1201.03367
Bitwuzla-MachBV Bitwuzla-MachBV unsat ✅ 150.38599 150.23957
BVDecide bv_decide unknown ❌ 1201.39137 1201.07379
bv_decide-nokernel unknown ❌ 1201.38550 1201.06658
cvc5 cvc5 unknown ❌ 1201.75344 1201.39570
SMTInterpol SMTInterpol unknown ❌ 1201.89577 3826.59868
Yices2 Yices2 unsat ✅ 450.29880 450.12903
Z3alpha Z3-alpha unknown ❌ 215.07819 858.62123
Z3 Z3-alpha-base unknown ❌ 1201.33789 1201.01529
Z3-Owl-base unknown ❌ 1201.31695 1201.05379
z3siri-base unknown ❌ 1201.37272 1201.08396
Z3-Owl Z3-Owl unknown ❌ 1201.76034 1200.99471