Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-8-8.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2

Benchmark
Size	98887
Compressed Size	15652
License	Creative Commons Attribution 4.0 International (CC-BY-4.0)
Category	industrial
First Occurrence	2023-07-06
Generated By	Sonja Gurtner and Mathias Fleury
Generated On	2023-02-19 00:00:00
Generator	Rosette
Dolmen OK	1
strict Dolmen OK	1
check-sat calls	1

Query 1

Status	unsat
Inferred Status	None
Size	98878
Compressed Size	15715
Max. Term Depth	3
Asserts	4
Declared Functions	0
Declared Constants	140
Declared Sorts	0
Defined Functions	0
Defined Recursive Functions	0
Defined Sorts	0
Constants	1696
Declared Datatypes	0

Symbols

Bool	1145	ite	683	not	78	or	100
and	269	=	671	BitVec	551	bvand	1
bvor	9	bvneg	23	bvadd	52	bvsmod	2
bvult	10	bvule	4	bvslt	1	bvsle	12
bvshl	36	bvlshr	19	bvashr	1