Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRAI-SAFE-112-1024.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size2803488
Compressed Size430877
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status unsat
Size 2803479
Compressed Size430881
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants55515
Declared Datatypes0

Symbols

Bool34673 ite7795 not8206 or10260
and10429 =5751 BitVec20842 bvand1
bvor9 bvneg1039 bvadd5132 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl5116 bvlshr1035 bvashr1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 0.67 (2/6) Bitwuzla Bitwuzla-fixed_default unsat ✅ 556.70200 556.67600
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.02000 1199.72000
STP STP 2022.4_default unsat ✅ 782.20100 782.03000
STP 2022.4_default unsat ✅ 732.72500 732.48100
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 6.09979 11.75520
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.02000 1199.90000
Z3-Owl z3-Owl-Final_default unknown ❌ 1200.01000 1199.88000
z3-Owl-Final_default unknown ❌ 1200.02000 1199.97000
SMT-COMP 2024 0.67 (2/6) Bitwuzla Bitwuzla unknown ❌ 1201.32062 1201.17447
cvc5 cvc5 unknown ❌ 1202.24146 1201.60191
SMTInterpol SMTInterpol unknown ❌ 1202.71933 1838.63001
STP STP unsat ✅ 764.53306 764.32621
Yices2 Yices2 unsat ✅ 1031.49811 1031.35777
Z3alpha Z3-alpha unknown ❌ 1201.72277 1201.29750
SMT-COMP 2025 0.78 (2/9) Bitwuzla Bitwuzla unknown ❌ 1201.35467 1201.09109
Bitwuzla-MachBV-base unknown ❌ 1201.36998 1201.01928
Bitwuzla-MachBV Bitwuzla-MachBV unsat ✅ 169.35879 169.20888
BVDecide bv_decide unknown ❌ 1201.38801 1201.11743
bv_decide-nokernel unknown ❌ 1201.44772 1201.05590
cvc5 cvc5 unknown ❌ 1202.25094 1201.54675
SMTInterpol SMTInterpol unknown ❌ 1201.87187 4181.12403
Yices2 Yices2 unsat ✅ 241.67922 241.52822
Z3alpha Z3-alpha unknown ❌ 215.32668 852.64031
Z3 Z3-alpha-base unknown ❌ 1201.37452 1201.12579
Z3-Owl-base unknown ❌ 1201.37590 1201.04288
z3siri-base unknown ❌ 1201.37141 1200.90878
Z3-Owl Z3-Owl unknown ❌ 1201.76488 1201.07954