Benchmark

non-incremental/QF_BV/20230221-oisc-gurtner/SRLI-SAFE-512-512.smt2

Publications: "A Formally Verified Reduction of the RV32I ISA", Sonja Gurtner
(https://epub.jku.at/obvulihs/content/titleinfo/8237703)

The benchmarks come from the master thesis from Sonja Gurtner "A Formally Verified Reduction of the
RV32I ISA" about translating RISC-V instructions using only memory operations, jump, and sub. The
translation was done by Rosette, a tool to translate constraints from a Racket-like language to the
SMT-LIB.

There are two parameters in the translation:

- the bitwidth we are considering

- the upper bound on the number of loop iterations (for
correctness, it must be larger than the bitwidth)

One limitation of the work is that the translation was verified one replacement at a time. We verify
that addition (RISC-V instruction add) can be replaced by two subtraction (RISC-V instruction sub),
but subsequently use the usual addition. Thanks to this, verification scales up to large
bitwidth. Otherwise, the verification of such nested instructions is very challenging.


Naming convention: <instruction_to_replace>[-nested]-<bitwidth>-<upper_bound>[-<counterexample-cause>.smt2
Benchmark
Size903076
Compressed Size138798
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2023-07-06
Generated BySonja Gurtner and Mathias Fleury
Generated On2023-02-19 00:00:00
GeneratorRosette
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status None
Size 903067
Compressed Size138804
Max. Term Depth3
Asserts 4
Declared Functions0
Declared Constants140
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants17647
Declared Datatypes0

Symbols

Bool9602 ite3186 not2065 or2586
and2755 =2169 BitVec8045 bvand1
bvor9 bvneg527 bvadd1551 bvsmod2
bvult10 bvule4 bvslt1 bvsle12
bvshl2044 bvlshr524

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2023 1.00 (0/6) Bitwuzla Bitwuzla-fixed_default unknown ❌ 1200.03000 1199.76000
cvc5 cvc5-default-2023-05-16-ea045f305_sq unknown ❌ 1200.03000 1199.51000
STP STP 2022.4_default unknown ❌ 1200.01000 1199.90000
STP 2022.4_default unknown ❌ 1200.02000 1199.85000
UltimateEliminator UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 4.59983 11.56110
Yices2 Yices 2 for SMTCOMP 2023_default unknown ❌ 1200.01000 1200.00000
Z3-Owl z3-Owl-Final_default unknown ❌ 1200.03000 1199.79000
z3-Owl-Final_default unknown ❌ 1200.02000 1199.76000
SMT-COMP 2024 1.00 (0/6) Bitwuzla Bitwuzla unknown ❌ 1201.31422 1201.17966
cvc5 cvc5 unknown ❌ 332.86442 334.48737
SMTInterpol SMTInterpol unknown ❌ 1202.75204 1927.24278
STP STP unknown ❌ 1201.30799 1200.85849
Yices2 Yices2 unknown ❌ 1201.30010 1201.07242
Z3alpha Z3-alpha unknown ❌ 339.92875 339.66058
SMT-COMP 2025 0.89 (1/9) Bitwuzla Bitwuzla unknown ❌ 1201.31637 1200.98361
Bitwuzla-MachBV-base unknown ❌ 1201.33964 1201.11193
Bitwuzla-MachBV Bitwuzla-MachBV unsat ✅ 496.71682 496.53291
BVDecide bv_decide unknown ❌ 1201.38704 1201.07718
bv_decide-nokernel unknown ❌ 1201.39584 1200.96411
cvc5 cvc5 unknown ❌ 238.78623 240.55733
SMTInterpol SMTInterpol unknown ❌ 1201.78467 3657.30957
Yices2 Yices2 unknown ❌ 1201.35616 1201.10679
Z3alpha Z3-alpha unknown ❌ 51.37817 203.37043
Z3 Z3-alpha-base unknown ❌ 1201.35206 1201.11630
Z3-Owl-base unknown ❌ 1201.31571 1201.01365
z3siri-base unknown ❌ 1201.33824 1200.93856
Z3-Owl Z3-Owl unknown ❌ 1201.76117 1201.19231