Benchmark
non-incremental/QF_S/2019-Jiang/slog/slog_stranger_4102_sink.smt2
Publication:
Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260.
| Benchmark |
|---|
| Size | 2754 |
| Compressed Size | 884 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2020-07-06 |
| Generated By | Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, and Jie-Hong R. Jiang |
| Generated On | 2019-02-28 00:00:00 |
| Generator | Stranger |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unknown |
| Inferred Status | sat |
| Size | 2746 |
| Compressed Size | 878 |
| Max. Term Depth | 4 |
| Asserts | 20 |
| Declared Functions | 0 |
| Declared Constants | 26 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
or | 1 |
= | 20 |
str.++ | 11 |
re.allchar | 2 |
str.to_re | 1 |
re.* | 2 |
re.++ | 2 |
str.in_re | 1 |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2022
|
|
CVC4 |
CVC4-sq-final_default |
sat ✅
|
0.08747
|
0.08783
|
| |
cvc5 |
cvc5-default-2022-07-02-b15e116-wrapped_sq |
sat ✅
|
0.17024
|
0.17073
|
| |
OSTRICH |
OSTRICH 1.2_def |
sat ✅
|
6.13252
|
17.85430
|
| |
Z3 |
z3-4.8.17_default |
sat ✅
|
0.06020
|
0.06193
|
| |
Z3string |
Z3str4_default |
sat ✅
|
0.07307
|
0.07306
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
sat ✅
|
0.36847
|
0.26879
|
| |
OSTRICH |
OSTRICH |
sat ✅
|
3.48910
|
9.31291
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
1140.48641
|
1140.12059
|
| |
Z3-Noodler |
Z3-Noodler |
sat ✅
|
0.26907
|
0.16853
|