Benchmark

non-incremental/QF_S/2019-Jiang/slog/slog_stranger_39_sink.smt2

Publication:
Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260.
Benchmark
Size1944
Compressed Size764
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2020-07-06
Generated ByHung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, and Jie-Hong R. Jiang
Generated On2019-02-28 00:00:00
GeneratorStranger
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unknown
Inferred Status sat
Size 1936
Compressed Size772
Max. Term Depth4
Asserts 8
Declared Functions0
Declared Constants11
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

=7 str.++2 str.replace3 re.allchar2
str.to_re1 re.*2 re.++2 str.in_re1

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2020 CVC4 CVC4-sq-final_default sat ✅ 0.02740 0.02767
Z3string Z3str4 SMTCOMP2020 v1.1_default sat ✅ 1.15518 1.86229
SMT-COMP 2022 CVC4 CVC4-sq-final_default sat ✅ 0.03078 0.03109
cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq sat ✅ 0.03796 0.03857
OSTRICH OSTRICH 1.2_def sat ✅ 13.05730 32.97430
Z3 z3-4.8.17_default sat ✅ 75.25760 75.23710
Z3string Z3str4_default sat ✅ 23.13270 23.13090
SMT-COMP 2023 cvc5 cvc5-default-2023-05-16-ea045f305_sq sat ✅ 0.02405 0.02454
cvc5-default-2022-07-02-b15e116-wrapped_sq sat ✅ 0.03752 0.03796
OSTRICH OSTRICH 1.3 SMT-COMP fixed_def sat ✅ 13.01550 31.62350
Z3alpha z3alpha_default sat ✅ 23.05440 23.05410
Z3-Noodler Z3-Noodler_default sat ✅ 0.15192 0.15186
Z3-Noodler_default sat ✅ 0.13588 0.13582
SMT-COMP 2024 cvc5 cvc5 sat ✅ 0.24401 0.14444
OSTRICH OSTRICH sat ✅ 12.45738 33.47657
Z3alpha Z3-alpha sat ✅ 1170.62568 1170.31733
Z3-Noodler Z3-Noodler sat ✅ 0.35962 0.25991