Benchmark
non-incremental/QF_S/2019-Jiang/slog/slog_stranger_57_sink.smt2
Publication:
Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260.
| Benchmark |
|---|
| Size | 1075 |
| Compressed Size | 557 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2020-07-06 |
| Generated By | Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, and Jie-Hong R. Jiang |
| Generated On | 2019-02-28 00:00:00 |
| Generator | Stranger |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unknown |
| Inferred Status | sat |
| Size | 1067 |
| Compressed Size | 555 |
| Max. Term Depth | 4 |
| Asserts | 4 |
| Declared Functions | 0 |
| Declared Constants | 5 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
= | 3 |
str.++ | 2 |
re.allchar | 2 |
str.to_re | 1 |
re.* | 2 |
re.++ | 2 |
str.in_re | 1 |
| |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2022
|
|
CVC4 |
CVC4-sq-final_default |
sat ✅
|
0.03510
|
0.03504
|
| |
cvc5 |
cvc5-default-2022-07-02-b15e116-wrapped_sq |
sat ✅
|
0.04672
|
0.04727
|
| |
OSTRICH |
OSTRICH 1.2_def |
sat ✅
|
2.08635
|
4.08383
|
| |
Z3 |
z3-4.8.17_default |
sat ✅
|
0.03710
|
0.03891
|
| |
Z3string |
Z3str4_default |
sat ✅
|
0.02145
|
0.02155
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
sat ✅
|
0.23659
|
0.13684
|
| |
OSTRICH |
OSTRICH |
sat ✅
|
2.09429
|
4.45900
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
0.35327
|
0.25347
|
| |
Z3-Noodler |
Z3-Noodler |
sat ✅
|
0.24410
|
0.14402
|