Benchmark
non-incremental/QF_S/2019-Jiang/slog/slog_stranger_2416_sink.smt2
Publication:
Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260.
| Benchmark |
|---|
| Size | 1005 |
| Compressed Size | 540 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2020-07-06 |
| Generated By | Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, and Jie-Hong R. Jiang |
| Generated On | 2019-02-28 00:00:00 |
| Generator | Stranger |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unknown |
| Inferred Status | sat |
| Size | 997 |
| Compressed Size | 540 |
| Max. Term Depth | 4 |
| Asserts | 3 |
| Declared Functions | 0 |
| Declared Constants | 4 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
= | 2 |
str.++ | 1 |
re.allchar | 2 |
str.to_re | 1 |
re.* | 2 |
re.++ | 2 |
str.in_re | 1 |
| |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2022
|
|
CVC4 |
CVC4-sq-final_default |
sat ✅
|
0.02529
|
0.02559
|
| |
cvc5 |
cvc5-default-2022-07-02-b15e116-wrapped_sq |
sat ✅
|
0.03312
|
0.03354
|
| |
OSTRICH |
OSTRICH 1.2_def |
sat ✅
|
1.93804
|
3.54615
|
| |
Z3 |
z3-4.8.17_default |
sat ✅
|
0.03441
|
0.03616
|
| |
Z3string |
Z3str4_default |
sat ✅
|
0.02013
|
0.02004
|
|
SMT-COMP 2025
|
|
cvc5 |
cvc5 |
sat ✅
|
0.27251
|
0.15563
|
| |
OSTRICH |
OSTRICH |
sat ✅
|
1.79179
|
3.91695
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
0.39318
|
0.27932
|
| |
Z3 |
Z3-alpha-base |
sat ✅
|
0.30650
|
0.18439
|
| |
|
Z3-Noodler-base |
sat ✅
|
0.30037
|
0.17252
|
| |
Z3-Noodler |
Z3-Noodler |
sat ✅
|
0.26816
|
0.15173
|
| |
|
Z3-Noodler-Mocha-base |
sat ✅
|
0.29239
|
0.16912
|
| |
Z3-Noodler-Mocha |
Z3-Noodler-Mocha |
sat ✅
|
0.30009
|
0.17234
|