Benchmark
non-incremental/QF_S/2019-Jiang/slog/slog_stranger_1641_sink.smt2
Publication:
Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260.
| Benchmark |
|---|
| Size | 1729 |
| Compressed Size | 717 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2020-07-06 |
| Generated By | Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, and Jie-Hong R. Jiang |
| Generated On | 2019-02-28 00:00:00 |
| Generator | Stranger |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | unknown |
| Inferred Status | sat |
| Size | 1721 |
| Compressed Size | 726 |
| Max. Term Depth | 4 |
| Asserts | 8 |
| Declared Functions | 0 |
| Declared Constants | 14 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
or | 1 |
= | 8 |
str.++ | 2 |
str.replace | 1 |
re.allchar | 2 |
str.to_re | 1 |
re.* | 2 |
re.++ | 2 |
str.in_re | 1 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2023
|
|
cvc5 |
cvc5-default-2023-05-16-ea045f305_sq |
sat ✅
|
0.02792
|
0.02846
|
| |
|
cvc5-default-2022-07-02-b15e116-wrapped_sq |
sat ✅
|
0.04033
|
0.04084
|
| |
OSTRICH |
OSTRICH 1.3 SMT-COMP fixed_def |
sat ✅
|
2.76712
|
6.76737
|
| |
Z3alpha |
z3alpha_default |
sat ✅
|
0.02019
|
0.02023
|
| |
Z3-Noodler |
Z3-Noodler_default |
sat ✅
|
0.03440
|
0.03436
|
| |
|
Z3-Noodler_default |
sat ✅
|
0.03314
|
0.03309
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
sat ✅
|
0.22722
|
0.12747
|
| |
OSTRICH |
OSTRICH |
sat ✅
|
2.28161
|
5.17928
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
0.28151
|
0.18171
|
| |
Z3-Noodler |
Z3-Noodler |
sat ✅
|
0.26000
|
0.16032
|