Benchmark
non-incremental/QF_UF/2018-Goel-hwbench/QF_UF_firewire_tree.3.prop2_ab_reg_max.smt2
Generated by the tool Averroes 2 (successor of [1]) which implements safety property
verification on hardware systems.
This SMT problem belongs to a set of SMT problems generated by applying Averroes 2
to benchmarks derived from [2-5].
A total of 412 systems (345 from [2], 19 from [3], 26 from [4], 22 from [5]) were
syntactically converted from their original formats (using [6, 7]), and given to
Averroes 2 to perform property checking with abstraction (wide bit-vectors -> terms,
wide operators -> UF) using SMT solvers [8, 9].
[1] Lee S., Sakallah K.A. (2014) Unbounded Scalable Verification Based on Approximate
Property-Directed Reachability and Datapath Abstraction. In: Biere A., Bloem R. (eds)
Computer Aided Verification. CAV 2014. Lecture Notes in Computer Science, vol 8559.
Springer, Cham
[2] http://fmv.jku.at/aiger/index.html#beem
[3] http://www.cs.cmu.edu/~modelcheck/vcegar
[4] http://www.cprover.org/hardware/v2c
[5] http://github.com/aman-goel/verilogbench
[6] http://www.clifford.at/yosys
[7] http://github.com/chengyinwu/V3
[8] http://github.com/Z3Prover/z3
[9] http://github.com/SRI-CSL/yices2
id: firewire_tree.3.prop2
query-maker: "Yices 2"
query-time: 20.206000 ms
query-class: abstract
query-category: oneshot
query-type: regular
status: sat
| Benchmark |
|---|
| Size | 1785447 |
| Compressed Size | 167542 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2018-07-14 |
| Generated By | Aman Goel (amangoel@umich.edu), Karem A. Sakallah (karem@umich.edu) |
| Generated On | 2018-04-06 00:00:00 |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 1785439 |
| Compressed Size | 167550 |
| Max. Term Depth | 3 |
| Asserts | 15066 |
| Declared Functions | 8 |
| Declared Constants | 23408 |
| Declared Sorts | 3 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
ite | 894 |
not | 7103 |
and | 6027 |
= | 15934 |
distinct | 2 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2018
|
0.14 (6/7) |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
sat ✅
|
1.41670
|
1.41673
|
| |
MathSAT |
mathsat-5.5.2-linux-x86_64-Main_default |
sat ✅
|
0.28442
|
0.28548
|
| |
OpenSMT |
opensmt2_default |
unknown ❌
|
49.18150
|
48.35470
|
| |
SMTInterpol |
SMTInterpol-2.5-19-g0d39cdee_default |
sat ✅
|
2.23813
|
6.14119
|
| |
veriT |
veriT_default |
sat ✅
|
1.15519
|
1.15525
|
| |
Yices2 |
Yices 2.6.0_default |
sat ✅
|
0.10565
|
0.10556
|
| |
Z3 |
z3-4.7.1_default |
sat ✅
|
0.33201
|
0.33189
|
|
SMT-COMP 2019
|
0.12 (7/8) |
Alt-Ergo |
Alt-Ergo-SMTComp-2019-wrapped-sq_default |
unknown ❌
|
2400.03000
|
3665.67000
|
| |
CVC4 |
CVC4-2019-06-03-d350fe1-wrapped-sq_default |
sat ✅
|
1.45923
|
1.45952
|
| |
OpenSMT |
OpenSMT-wrapped-sq_default |
sat ✅
|
3.57462
|
3.57439
|
| |
Par4 |
Par4-wrapped-sq_default |
sat ✅
|
0.07794
|
0.00626
|
| |
SMTInterpol |
smtinterpol-2.5-514-wrapped-sq_default |
sat ✅
|
2.02564
|
5.59167
|
| |
veriT |
veriT-wrapped-sq_default |
sat ✅
|
1.14355
|
1.14373
|
| |
Yices2 |
Yices 2.6.0_default |
sat ✅
|
0.07317
|
0.07308
|
| |
|
Yices 2.6.2-wrapped-sq_default |
sat ✅
|
0.07248
|
0.07244
|
| |
Z3 |
z3-4.8.4-d6df51951f4c-wrapped-sq_default |
sat ✅
|
0.32056
|
0.32053
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
sat ✅
|
1.49783
|
1.39701
|
| |
OpenSMT |
OpenSMT |
sat ✅
|
1.09666
|
0.99666
|
| |
plat-smt |
plat-smt |
sat ✅
|
0.28095
|
0.18107
|
| |
SMTInterpol |
SMTInterpol |
sat ✅
|
2.68941
|
8.23087
|
| |
Yices2 |
Yices2 |
sat ✅
|
0.32182
|
0.22099
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
0.74582
|
0.64598
|
|
SMT-COMP 2025
|
|
cvc5 |
cvc5 |
sat ✅
|
1.19540
|
1.07649
|
| |
OpenSMT |
OpenSMT |
sat ✅
|
1.29552
|
1.17976
|
| |
SMTInterpol |
SMTInterpol |
sat ✅
|
2.32636
|
6.76762
|
| |
Yices2 |
Yices2 |
sat ✅
|
0.29533
|
0.17616
|