Benchmark

non-incremental/QF_UF/2018-Goel-hwbench/QF_UF_firewire_tree.1.prop3_ab_cti_max.smt2

Generated by the tool Averroes 2 (successor of [1]) which implements safety property
verification on hardware systems.

This SMT problem belongs to a set of SMT problems generated by applying Averroes 2
to benchmarks derived from [2-5].

A total of 412 systems (345 from [2], 19 from [3], 26 from [4], 22 from [5]) were
syntactically converted from their original formats (using [6, 7]), and given to 
Averroes 2 to perform property checking with abstraction (wide bit-vectors -> terms, 
wide operators -> UF) using SMT solvers [8, 9].

[1] Lee S., Sakallah K.A. (2014) Unbounded Scalable Verification Based on Approximate
Property-Directed Reachability and Datapath Abstraction. In: Biere A., Bloem R. (eds)
Computer Aided Verification. CAV 2014. Lecture Notes in Computer Science, vol 8559.
Springer, Cham
[2] http://fmv.jku.at/aiger/index.html#beem
[3] http://www.cs.cmu.edu/~modelcheck/vcegar
[4] http://www.cprover.org/hardware/v2c
[5] http://github.com/aman-goel/verilogbench
[6] http://www.clifford.at/yosys
[7] http://github.com/chengyinwu/V3
[8] http://github.com/Z3Prover/z3
[9] http://github.com/SRI-CSL/yices2

id: firewire_tree.1.prop3
query-maker: "Yices 2"
query-time: 18.275000 ms
query-class: abstract
query-category: oneshot
query-type: cti
status: sat
Benchmark
Size1785298
Compressed Size167199
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2018-07-14
Generated ByAman Goel (amangoel@umich.edu), Karem A. Sakallah (karem@umich.edu)
Generated On2018-04-06 00:00:00
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status sat
Inferred Status sat
Size 1785290
Compressed Size167207
Max. Term Depth3
Asserts 15034
Declared Functions8
Declared Constants23464
Declared Sorts 3
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

ite894 not7117 and6035 =15839
distinct4

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2018 0.14 (6/7) CVC4 master-2018-06-10-b19c840-competition-default_default sat ✅ 17.69470 17.69320
MathSAT mathsat-5.5.2-linux-x86_64-Main_default sat ✅ 0.31473 0.31587
OpenSMT opensmt2_default unknown ❌ 48.39290 47.68500
SMTInterpol SMTInterpol-2.5-19-g0d39cdee_default sat ✅ 1.99592 5.61929
veriT veriT_default sat ✅ 1.15510 1.15524
Yices2 Yices 2.6.0_default sat ✅ 0.08627 0.08619
Z3 z3-4.7.1_default sat ✅ 2.48949 2.48880
SMT-COMP 2022 cvc5 cvc5-default-2022-07-02-b15e116-wrapped_sq sat ✅ 5.33348 5.32887
MathSAT MathSAT-5.6.8_default sat ✅ 0.33837 0.33831
veriT veriT_default sat ✅ 1.16839 1.16842
Yices2 Yices 2.6.2 for SMTCOMP 2021_default sat ✅ 0.11611 0.11604
Z3 z3-4.8.17_default sat ✅ 0.81147 0.81341
z3-4.8.11_default sat ✅ 2.58151 2.58139
SMT-COMP 2023 cvc5 cvc5-default-2023-05-16-ea045f305_sq sat ✅ 3.24538 3.24495
OpenSMT OpenSMT a78dcf01_default sat ✅ 2.24741 2.24753
SMTInterpol smtinterpol-2.5-1272-g2d6d356c_default sat ✅ 2.72773 8.19195
Yices2 Yices 2 for SMTCOMP 2023_default sat ✅ 0.11771 0.11752
Yices 2.6.2 for SMTCOMP 2021_default sat ✅ 0.11454 0.11453