Benchmark

non-incremental/QF_UF/2018-Goel-hwbench/QF_UF_firewire_tree.3.prop2_ab_cti_max.smt2

Generated by the tool Averroes 2 (successor of [1]) which implements safety property
verification on hardware systems.

This SMT problem belongs to a set of SMT problems generated by applying Averroes 2
to benchmarks derived from [2-5].

A total of 412 systems (345 from [2], 19 from [3], 26 from [4], 22 from [5]) were
syntactically converted from their original formats (using [6, 7]), and given to 
Averroes 2 to perform property checking with abstraction (wide bit-vectors -> terms, 
wide operators -> UF) using SMT solvers [8, 9].

[1] Lee S., Sakallah K.A. (2014) Unbounded Scalable Verification Based on Approximate
Property-Directed Reachability and Datapath Abstraction. In: Biere A., Bloem R. (eds)
Computer Aided Verification. CAV 2014. Lecture Notes in Computer Science, vol 8559.
Springer, Cham
[2] http://fmv.jku.at/aiger/index.html#beem
[3] http://www.cs.cmu.edu/~modelcheck/vcegar
[4] http://www.cprover.org/hardware/v2c
[5] http://github.com/aman-goel/verilogbench
[6] http://www.clifford.at/yosys
[7] http://github.com/chengyinwu/V3
[8] http://github.com/Z3Prover/z3
[9] http://github.com/SRI-CSL/yices2

id: firewire_tree.3.prop2
query-maker: "Yices 2"
query-time: 69.702000 ms
query-class: abstract
query-category: oneshot
query-type: cti
status: sat
Benchmark
Size1781176
Compressed Size167340
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2018-07-14
Generated ByAman Goel (amangoel@umich.edu), Karem A. Sakallah (karem@umich.edu)
Generated On2018-04-06 00:00:00
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status sat
Inferred Status sat
Size 1781168
Compressed Size167353
Max. Term Depth3
Asserts 15000
Declared Functions8
Declared Constants23418
Declared Sorts 3
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

ite894 not7108 and6030 =15792
distinct4

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2018 0.14 (6/7) CVC4 master-2018-06-10-b19c840-competition-default_default sat ✅ 17.99850 17.99780
MathSAT mathsat-5.5.2-linux-x86_64-Main_default sat ✅ 0.31313 0.31415
OpenSMT opensmt2_default unknown ❌ 47.13010 46.35520
SMTInterpol SMTInterpol-2.5-19-g0d39cdee_default sat ✅ 1.95429 5.54828
veriT veriT_default sat ✅ 1.20667 1.20666
Yices2 Yices 2.6.0_default sat ✅ 0.10972 0.10961
Z3 z3-4.7.1_default sat ✅ 2.46530 2.46515
SMT-COMP 2019 0.12 (7/8) Alt-Ergo Alt-Ergo-SMTComp-2019-wrapped-sq_default unknown ❌ 2400.09000 2612.74000
CVC4 CVC4-2019-06-03-d350fe1-wrapped-sq_default sat ✅ 15.23390 15.23300
OpenSMT OpenSMT-wrapped-sq_default sat ✅ 14.81000 14.80730
Par4 Par4-wrapped-sq_default sat ✅ 0.11747 0.00612
SMTInterpol smtinterpol-2.5-514-wrapped-sq_default sat ✅ 2.14880 6.22700
veriT veriT-wrapped-sq_default sat ✅ 1.14356 1.14386
Yices2 Yices 2.6.0_default sat ✅ 0.11147 0.11143
Yices 2.6.2-wrapped-sq_default sat ✅ 0.11055 0.11055
Z3 z3-4.8.4-d6df51951f4c-wrapped-sq_default sat ✅ 2.45986 2.45975
SMT-COMP 2023 cvc5 cvc5-default-2023-05-16-ea045f305_sq sat ✅ 3.19362 3.19380
OpenSMT OpenSMT a78dcf01_default sat ✅ 2.26896 2.26753
SMTInterpol smtinterpol-2.5-1272-g2d6d356c_default sat ✅ 2.89557 8.31421
Yices2 Yices 2 for SMTCOMP 2023_default sat ✅ 0.08979 0.08975
Yices 2.6.2 for SMTCOMP 2021_default sat ✅ 0.11097 0.10961
SMT-COMP 2025 cvc5 cvc5 sat ✅ 1.81206 1.68584
OpenSMT OpenSMT sat ✅ 1.38794 1.26169
SMTInterpol SMTInterpol sat ✅ 2.25515 6.53718
Yices2 Yices2 sat ✅ 0.32217 0.19404