Benchmark
non-incremental/QF_UF/2018-Goel-hwbench/QF_UF_firewire_tree.4.prop3_ab_cti_max.smt2
Generated by the tool Averroes 2 (successor of [1]) which implements safety property
verification on hardware systems.
This SMT problem belongs to a set of SMT problems generated by applying Averroes 2
to benchmarks derived from [2-5].
A total of 412 systems (345 from [2], 19 from [3], 26 from [4], 22 from [5]) were
syntactically converted from their original formats (using [6, 7]), and given to
Averroes 2 to perform property checking with abstraction (wide bit-vectors -> terms,
wide operators -> UF) using SMT solvers [8, 9].
[1] Lee S., Sakallah K.A. (2014) Unbounded Scalable Verification Based on Approximate
Property-Directed Reachability and Datapath Abstraction. In: Biere A., Bloem R. (eds)
Computer Aided Verification. CAV 2014. Lecture Notes in Computer Science, vol 8559.
Springer, Cham
[2] http://fmv.jku.at/aiger/index.html#beem
[3] http://www.cs.cmu.edu/~modelcheck/vcegar
[4] http://www.cprover.org/hardware/v2c
[5] http://github.com/aman-goel/verilogbench
[6] http://www.clifford.at/yosys
[7] http://github.com/chengyinwu/V3
[8] http://github.com/Z3Prover/z3
[9] http://github.com/SRI-CSL/yices2
id: firewire_tree.4.prop3
query-maker: "Yices 2"
query-time: 38.132000 ms
query-class: abstract
query-category: oneshot
query-type: cti
status: sat
| Benchmark |
|---|
| Size | 2367489 |
| Compressed Size | 219330 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2018-07-14 |
| Generated By | Aman Goel (amangoel@umich.edu), Karem A. Sakallah (karem@umich.edu) |
| Generated On | 2018-04-06 00:00:00 |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 2367481 |
| Compressed Size | 219337 |
| Max. Term Depth | 3 |
| Asserts | 19778 |
| Declared Functions | 8 |
| Declared Constants | 30913 |
| Declared Sorts | 3 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
ite | 1260 |
not | 9255 |
and | 7929 |
= | 20879 |
distinct | 4 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2018
|
0.14 (6/7) |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
sat ✅
|
32.48360
|
32.48310
|
| |
MathSAT |
mathsat-5.5.2-linux-x86_64-Main_default |
sat ✅
|
0.44154
|
0.44261
|
| |
OpenSMT |
opensmt2_default |
unknown ❌
|
97.10850
|
95.33990
|
| |
SMTInterpol |
SMTInterpol-2.5-19-g0d39cdee_default |
sat ✅
|
3.15622
|
8.99432
|
| |
veriT |
veriT_default |
sat ✅
|
1.92427
|
1.92431
|
| |
Yices2 |
Yices 2.6.0_default |
sat ✅
|
0.16839
|
0.16829
|
| |
Z3 |
z3-4.7.1_default |
sat ✅
|
4.65111
|
4.65082
|
|
SMT-COMP 2021
|
|
MathSAT |
mathsat-5.6.6_default |
sat ✅
|
0.46947
|
0.46937
|
| |
Par4 |
Par4-wrapped-sq_default |
sat ✅
|
0.17787
|
0.00634
|
| |
SMTInterpol |
smtinterpol-2.5-823-g881e8631_default |
sat ✅
|
3.65035
|
10.17530
|
| |
veriT |
veriT_default |
sat ✅
|
1.99983
|
2.00006
|
| |
Yices2 |
Yices 2.6.2 bug fix_default |
sat ✅
|
0.17388
|
0.17385
|
| |
|
Yices 2.6.2 for SMTCOMP2020_default |
sat ✅
|
0.17639
|
0.17634
|
| |
Z3 |
z3-4.8.11_default |
sat ✅
|
5.25019
|
5.25054
|
| |
|
z3-4.8.8_default |
sat ✅
|
5.70883
|
5.70619
|
|
SMT-COMP 2023
|
|
cvc5 |
cvc5-default-2023-05-16-ea045f305_sq |
sat ✅
|
5.92099
|
5.91598
|
| |
OpenSMT |
OpenSMT a78dcf01_default |
sat ✅
|
3.88209
|
3.88221
|
| |
SMTInterpol |
smtinterpol-2.5-1272-g2d6d356c_default |
sat ✅
|
3.62495
|
10.79220
|
| |
Yices2 |
Yices 2 for SMTCOMP 2023_default |
sat ✅
|
0.13572
|
0.13565
|
| |
|
Yices 2.6.2 for SMTCOMP 2021_default |
sat ✅
|
0.13170
|
0.13164
|
|
SMT-COMP 2025
|
|
cvc5 |
cvc5 |
sat ✅
|
2.85517
|
2.73731
|
| |
OpenSMT |
OpenSMT |
sat ✅
|
3.53496
|
3.40814
|
| |
SMTInterpol |
SMTInterpol |
sat ✅
|
2.98925
|
8.49658
|
| |
Yices2 |
Yices2 |
sat ✅
|
0.36013
|
0.23259
|