Benchmark
non-incremental/QF_UF/2018-Goel-hwbench/QF_UF_firewire_tree.5.prop2_ab_reg_max.smt2
Generated by the tool Averroes 2 (successor of [1]) which implements safety property
verification on hardware systems.
This SMT problem belongs to a set of SMT problems generated by applying Averroes 2
to benchmarks derived from [2-5].
A total of 412 systems (345 from [2], 19 from [3], 26 from [4], 22 from [5]) were
syntactically converted from their original formats (using [6, 7]), and given to
Averroes 2 to perform property checking with abstraction (wide bit-vectors -> terms,
wide operators -> UF) using SMT solvers [8, 9].
[1] Lee S., Sakallah K.A. (2014) Unbounded Scalable Verification Based on Approximate
Property-Directed Reachability and Datapath Abstraction. In: Biere A., Bloem R. (eds)
Computer Aided Verification. CAV 2014. Lecture Notes in Computer Science, vol 8559.
Springer, Cham
[2] http://fmv.jku.at/aiger/index.html#beem
[3] http://www.cs.cmu.edu/~modelcheck/vcegar
[4] http://www.cprover.org/hardware/v2c
[5] http://github.com/aman-goel/verilogbench
[6] http://www.clifford.at/yosys
[7] http://github.com/chengyinwu/V3
[8] http://github.com/Z3Prover/z3
[9] http://github.com/SRI-CSL/yices2
id: firewire_tree.5.prop2
query-maker: "Yices 2"
query-time: 65.580000 ms
query-class: abstract
query-category: oneshot
query-type: regular
status: sat
| Benchmark |
| Size | 4643062 |
| Compressed Size | 409713 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2018-07-14 |
| Generated By | Aman Goel (amangoel@umich.edu), Karem A. Sakallah (karem@umich.edu) |
| Generated On | 2018-04-06 00:00:00 |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 4643054 |
| Compressed Size | 409720 |
| Max. Term Depth | 3 |
| Asserts | 38189 |
| Declared Functions | 8 |
| Declared Constants | 59559 |
| Declared Sorts | 3 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
ite | 2850 |
not | 17263 |
and | 15115 |
= | 40738 |
distinct | 2 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2018
|
0.14 (6/7) |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
sat ✅
|
5.20318
|
5.20291
|
| |
MathSAT |
mathsat-5.5.2-linux-x86_64-Main_default |
sat ✅
|
1.02685
|
1.02791
|
| |
OpenSMT |
opensmt2_default |
unknown ❌
|
621.98100
|
615.13400
|
| |
SMTInterpol |
SMTInterpol-2.5-19-g0d39cdee_default |
sat ✅
|
4.50187
|
11.06410
|
| |
veriT |
veriT_default |
sat ✅
|
7.28322
|
7.28233
|
| |
Yices2 |
Yices 2.6.0_default |
sat ✅
|
0.52184
|
0.52168
|
| |
Z3 |
z3-4.7.1_default |
sat ✅
|
1.32595
|
1.32558
|
|
SMT-COMP 2019
|
0.12 (7/8) |
Alt-Ergo |
Alt-Ergo-SMTComp-2019-wrapped-sq_default |
unknown ❌
|
2400.05000
|
6209.57000
|
| |
CVC4 |
CVC4-2019-06-03-d350fe1-wrapped-sq_default |
sat ✅
|
5.44404
|
5.44405
|
| |
OpenSMT |
OpenSMT-wrapped-sq_default |
sat ✅
|
118.48300
|
118.43500
|
| |
Par4 |
Par4-wrapped-sq_default |
sat ✅
|
0.34886
|
0.00689
|
| |
SMTInterpol |
smtinterpol-2.5-514-wrapped-sq_default |
sat ✅
|
4.62712
|
13.57620
|
| |
veriT |
veriT-wrapped-sq_default |
sat ✅
|
7.41039
|
7.40999
|
| |
Yices2 |
Yices 2.6.0_default |
sat ✅
|
0.33804
|
0.33799
|
| |
|
Yices 2.6.2-wrapped-sq_default |
sat ✅
|
0.34104
|
0.34102
|
| |
Z3 |
z3-4.8.4-d6df51951f4c-wrapped-sq_default |
sat ✅
|
1.23808
|
1.23807
|
|
SMT-COMP 2020
|
0.27 (8/11) |
Alt-Ergo |
Alt-Ergo-SMTComp-2020_default |
unknown ❌
|
1200.05000
|
1990.80000
|
| |
CVC4 |
CVC4-sq-final_default |
sat ✅
|
5.83394
|
5.83396
|
| |
MathSAT |
MathSAT5_default.sh |
sat ✅
|
0.99520
|
0.99456
|
| |
OpenSMT |
OpenSMT_default |
sat ✅
|
13.33980
|
13.33890
|
| |
Par4 |
Par4-wrapped-sq_default |
sat ✅
|
0.54985
|
0.00649
|
| |
SMTInterpol |
smtinterpol-2.5-679-gacfde87a_default |
sat ✅
|
4.49779
|
12.39820
|
| |
veriT |
veriT_default |
sat ✅
|
6.06082
|
6.06001
|
| |
Yices2 |
Yices 2.6.2 bug fix_default |
sat ✅
|
0.56072
|
0.56062
|
| |
Z3 |
z3-4.8.8_default |
sat ✅
|
1.43734
|
1.43725
|
|
SMT-COMP 2024
|
|
cvc5 |
cvc5 |
sat ✅
|
5.43259
|
5.32922
|
| |
OpenSMT |
OpenSMT |
sat ✅
|
4.15232
|
4.05231
|
| |
plat-smt |
plat-smt |
sat ✅
|
0.43938
|
0.33879
|
| |
SMTInterpol |
SMTInterpol |
sat ✅
|
5.27945
|
16.30339
|
| |
Yices2 |
Yices2 |
sat ✅
|
0.52651
|
0.42675
|
| |
Z3alpha |
Z3-alpha |
sat ✅
|
1.73970
|
1.63975
|
|
SMT-COMP 2025
|
|
cvc5 |
cvc5 |
sat ✅
|
3.34358
|
3.22269
|
| |
OpenSMT |
OpenSMT |
sat ✅
|
7.02624
|
6.89352
|
| |
SMTInterpol |
SMTInterpol |
sat ✅
|
4.49605
|
13.06452
|
| |
Yices2 |
Yices2 |
sat ✅
|
0.61353
|
0.49322
|