Benchmark

non-incremental/BV/20170501-Heizmann-UltimateAutomizer/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call.i_2400.smt2

Generated by the tool Ultimate Automizer [1,2] which implements 
an automata theoretic approach [3] to software verification.

This SMT script belongs to a set of SMT scripts that was generated by 
applying Ultimate Automizer to benchmarks [4] from the SV-COMP 2017 [5,6].

This script might _not_ contain all SMT commands that are used by 
Ultimate Automizer. In order to satisfy the restrictions of
the SMT-COMP we have to drop e.g., the commands for getting
values (resp. models), unsatisfiable cores and interpolants.

2017-05-01, Matthias Heizmann (heizmann@informatik.uni-freiburg.de)


[1] https://ultimate.informatik.uni-freiburg.de/automizer/
[2] Matthias Heizmann, Yu-Wen Chen, Daniel Dietsch, Marius Greitschus, 
Alexander Nutz, Betim Musa, Claus Schätzle, Christian Schilling, 
Frank Schüssele, Andreas Podelski:
Ultimate Automizer with an On-Demand Construction of Floyd-Hoare 
Automata - (Competition Contribution). TACAS (2) 2017: 394-398
[3] Matthias Heizmann, Jochen Hoenicke, Andreas Podelski: Software Model 
Checking for People Who Love Automata. CAV 2013:36-52
[4] https://github.com/sosy-lab/sv-benchmarks
[5] Dirk Beyer: Software Verification with Validation of Results - 
(Report on SV-COMP 2017). TACAS (2) 2017: 331-349
[6] https://sv-comp.sosy-lab.org/2017/
Benchmark
Size7025
Compressed Size1445
License Creative Commons Attribution 4.0 International (CC-BY-4.0)
Categoryindustrial
First Occurrence2017-07-23
Generated By
Generated On
Generator
Dolmen OK1
strict Dolmen OK1
check-sat calls1
Query 1
Status unsat
Inferred Status unsat
Size 7017
Compressed Size1446
Max. Term Depth16
Asserts 3
Declared Functions0
Declared Constants2
Declared Sorts 0
Defined Functions0
Defined Recursive Functions 0
Defined Sorts0
Constants0
Declared Datatypes0

Symbols

not37 or6 and1 =1
forall6 BitVec18 bvadd19 bvmul18
bvsub18 bvsle36 bvsge7 zero_extend54
sign_extend54

Evaluations

Evaluation Rating Solver Variant Result Wallclock CPU Time
SMT-COMP 2017 Boolector Boolector SMT17 final boolector unsat ✅ 0.77953 1.44752
CVC4 CVC4-smtcomp2017-main default unsat ✅ 0.83068 0.82973
Q3B Q3B default unsat ✅ 11.44920 33.88000
Z3 z3-4.5.0 default unsat ✅ 0.68759 0.68673
SMT-COMP 2018 Boolector Boolector_default unsat ✅ 1.87895 3.72260
CVC4 master-2018-06-10-b19c840-competition-default_default unsat ✅ 4.99619 4.99612
Q3B Q3B_default unsat ✅ 1.98243 5.82759
Z3 z3-4.7.1_default unsat ✅ 0.56387 0.56377
SMT-COMP 2021 0.50 (2/4) Par4 Par4-wrapped-sq_default unsat ✅ 0.59172 2.23000
UltimateEliminator UltimateEliminator+MathSAT-5.6.6_default unknown ❌ 3.72932 7.93580
YicesQS yices-QS-2021-06-13under10_default unknown ❌ 1200.02000 1199.74000
Z3 z3-4.8.11_default unsat ✅ 0.50316 0.50313
SMT-COMP 2023 0.50 (3/6) Bitwuzla Bitwuzla-fixed_default unsat ✅ 2.25023 2.25007
cvc5 cvc5-default-2023-05-16-ea045f305_sq unsat ✅ 0.56346 0.55842
Par4 Par4-wrapped-sq_default unsat ✅ 0.80490 3.02000
Q3B Q3B_default unknown ❌ 1200.02000 3597.30000
UltimateEliminator UltimateEliminator+MathSAT-5.6.9_default unknown ❌ 3.25091 6.48087
UltimateIntBlastingWrapper+SMTInterpol_default unknown ❌ 1200.04000 1239.14000
YicesQS yicesQS-2022-07-02-optim-under10_default unknown ❌ 1200.01000 1199.79000
SMT-COMP 2024 0.20 (4/5) Bitwuzla Bitwuzla unsat ✅ 2.04020 1.93953
cvc5 cvc5 unsat ✅ 0.88036 0.77921
SMTInterpol SMTInterpol unknown ❌ 1201.73037 1224.34732
YicesQS YicesQS unsat ✅ 1.04776 0.94793
Z3alpha Z3-alpha unsat ✅ 17.98569 17.88514