Benchmark
non-incremental/BV/2017-Preiner-scholl-smt08/model/model_5_48.smt2
Scholl, Christoph; Disch, Stefan; Pigorsch, Florian and Kupferschmid,
Stefan; Using an SMT Solver and Craig Interpolation to Detect and Remove
Redundant Linear Constraints in Representations of Non-Convex Polyhedra.
Proceedings of 6th International Workshop on Satisfiability Modulo
Theories, Princeton, USA, July 2008.
<http://abs.informatik.uni-freiburg.de/smtbench/>
Translated to BV by Mathias Preiner.
| Benchmark |
|---|
| Size | 8536 |
| Compressed Size | 2280 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | industrial |
| First Occurrence | 2017-07-23 |
| Generated By | — |
| Generated On | — |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 8528 |
| Compressed Size | 2302 |
| Max. Term Depth | 103 |
| Asserts | 1 |
| Declared Functions | 0 |
| Declared Constants | 10 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
not | 201 |
or | 2 |
and | 244 |
forall | 1 |
exists | 1 |
let | 65 |
BitVec | 2 |
bvneg | 13 |
bvadd | 7 |
bvmul | 13 |
bvsdiv | 6 |
bvslt | 1 |
bvsle | 22 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2017
|
|
Boolector |
Boolector SMT17 final boolector |
sat ✅
|
0.15845
|
0.30264
|
| |
CVC4 |
CVC4-smtcomp2017-main default |
sat ✅
|
0.12820
|
0.12765
|
| |
Q3B |
Q3B default |
sat ✅
|
0.42197
|
0.60459
|
| |
Z3 |
z3-4.5.0 default |
sat ✅
|
0.04083
|
0.04015
|
|
SMT-COMP 2018
|
|
Boolector |
Boolector_default |
sat ✅
|
0.17879
|
0.34314
|
| |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
sat ✅
|
0.10160
|
0.10178
|
| |
Q3B |
Q3B_default |
sat ✅
|
0.22974
|
0.49306
|
| |
Z3 |
z3-4.7.1_default |
sat ✅
|
0.04428
|
0.04418
|