Benchmark
non-incremental/BV/2017-Preiner-scholl-smt08/RND/RND_4_8.smt2
Scholl, Christoph; Disch, Stefan; Pigorsch, Florian and Kupferschmid,
Stefan; Using an SMT Solver and Craig Interpolation to Detect and Remove
Redundant Linear Constraints in Representations of Non-Convex Polyhedra.
Proceedings of 6th International Workshop on Satisfiability Modulo
Theories, Princeton, USA, July 2008.
<http://abs.informatik.uni-freiburg.de/smtbench/>
Translated to BV by Mathias Preiner.
| Benchmark |
|---|
| Size | 2113 |
| Compressed Size | 789 |
| License |
Creative Commons Attribution 4.0 International
(CC-BY-4.0)
|
| Category | random |
| First Occurrence | 2017-07-23 |
| Generated By | — |
| Generated On | — |
| Generator | — |
| Dolmen OK | 1 |
| strict Dolmen OK | 1 |
| check-sat calls | 1 |
| Status | sat |
| Inferred Status | sat |
| Size | 2105 |
| Compressed Size | 796 |
| Max. Term Depth | 14 |
| Asserts | 1 |
| Declared Functions | 0 |
| Declared Constants | 4 |
| Declared Sorts | 0 |
| Defined Functions | 0 |
| Defined Recursive Functions | 0 |
| Defined Sorts | 0 |
| Constants | 0 |
| Declared Datatypes | 0 |
Symbols
not | 3 |
or | 5 |
and | 4 |
= | 6 |
forall | 1 |
exists | 3 |
BitVec | 4 |
bvneg | 20 |
bvadd | 18 |
bvmul | 28 |
bvslt | 1 |
bvsgt | 2 |
bvsge | 1 |
| | | | | |
Evaluations
| Evaluation |
Rating |
Solver |
Variant |
Result |
Wallclock |
CPU Time |
|
SMT-COMP 2017
|
|
Boolector |
Boolector SMT17 final boolector |
sat ✅
|
1.45089
|
1.48786
|
| |
CVC4 |
CVC4-smtcomp2017-main default |
sat ✅
|
0.39228
|
0.39088
|
| |
Q3B |
Q3B default |
sat ✅
|
23.00750
|
68.41000
|
| |
Z3 |
z3-4.5.0 default |
sat ✅
|
0.04205
|
0.04091
|
|
SMT-COMP 2018
|
|
Boolector |
Boolector_default |
sat ✅
|
0.05473
|
0.09237
|
| |
CVC4 |
master-2018-06-10-b19c840-competition-default_default |
sat ✅
|
0.46760
|
0.46779
|
| |
Q3B |
Q3B_default |
sat ✅
|
0.06782
|
0.15852
|
| |
Z3 |
z3-4.7.1_default |
sat ✅
|
0.04635
|
0.04623
|